Chittaranjan A. Mandal

Publication Activity (10 Years)

Years Active: 1992-2022
Publications (10 Years): 14

Top Topics

Monotonicity Constraints

Connected Dominating Set

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal, Holger Giese
Translation validation of coloured Petri net models of programs on integers. Acta Informatica 59 (6) (2022)
Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
Exploring the Scope of Unconstrained Via Minimization by Recursive Floorplan Bipartitioning. CoRR (2018)
Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
STAIRoute: Early Global Routing using Monotone Staircases for Congestion Reduction. CoRR (2018)
Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
Early Routability Assessment in VLSI Floorplans: A Generalized Routing Model. CoRR (2018)
Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar
An Equivalence Checking Framework for Array-Intensive Programs. ATVA (2017)
Jasaswi Prasad Mohanty, Chittaranjan A. Mandal, Chris Reade
Distributed construction of minimum Connected Dominating Set in wireless sensor network using two-hop information. Comput. Networks 123 (2017)
Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal
Deriving bisimulation relations from path based equivalence checkers. Formal Aspects Comput. 29 (2) (2017)
Soumyadip Bandyopadhyay, Santonu Sarkar, Dipankar Sarkar, Chittaranjan A. Mandal
SamaTulyata: An Efficient Path Based Equivalence Checking Tool. ATVA (2017)
Jasaswi Prasad Mohanty, Chittaranjan A. Mandal, Chris Reade, Ariyam Das
Construction of minimum connected dominating set in wireless sensor networks using pseudo dominating set. Ad Hoc Networks 42 (2016)
Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar
Translation validation of loop and arithmetic transformations in the presence of recurrences. LCTES (2016)
Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal
An efficient path based equivalence checking for Petri net based models of programs. ISEC (2016)
Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
A Novel EPE Aware Hybrid Global Route Planner after Floorplanning. VLSI Design (2016)
Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
An early global routing framework for uniform wire distribution in SoCs. SoCC (2016)
Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal, Kunal Banerjee, Krishnam Raju Duddu
A Path Construction Algorithm for Translation Validation Using PRES+ Models. Parallel Process. Lett. 26 (2) (2016)
Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
A New Method for Defining Monotone Staircases in VLSI Floorplans. ISVLSI (2015)
Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar
A translation validation framework for symbolic value propagation based equivalence checking of FSMDAs. SCAM (2015)
Soumyadip Bandyopadhyay, Dipankar Sarkar, Kunal Banerjee, Chittaranjan A. Mandal
A Path-based Equivalence Checking Method for Petri Net based Models of Programs. ICSOFT-EA (2015)
Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal
Validating SPARK: High Level Synthesis Compiler. ISVLSI (2015)
Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar
Translation Validation of Transformations of Embedded System Specifications Using Equivalence Checking. ISVLSI (2015)
K. K. Sharma, Kunal Banerjee, Chittaranjan A. Mandal
Establishing Equivalence of Expressions: An Automated Evaluator Designer's Perspective. MIKE (2015)
Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal
Poster: An Efficient Equivalence Checking Method for Petri Net Based Models of Programs. ICSE (2) (2015)
K. K. Sharma, Kunal Banerjee, Chittaranjan A. Mandal
Determining Equivalence of Expressions: An Automated Evaluator's Perspective. T4E (2015)
Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar
Extending the scope of translation validation by augmenting path based equivalence checkers with SMT solvers. VDAT (2014)
Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal
Extending the FSMD Framework for Validating Code Motions of Array-Handling Programs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (12) (2014)
Partha De, Kunal Banerjee, Chittaranjan A. Mandal, Debdeep Mukhopadhyay
Circuits and Synthesis Mechanism for Hardware Design to Counter Power Analysis Attacks. DSD (2014)
Partha De, Kunal Banerjee, Chittaranjan A. Mandal
A BDD based secure hardware design method to guard against power analysis attacks. VDAT (2014)
Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
Global Routing Using Monotone Staircases with Minimal Bends. VLSI Design (2014)
Kunal Banerjee, Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal
Verification of Code Motion Techniques Using Value Propagation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (8) (2014)
Partha De, Kunal Banerjee, Chittaranjan A. Mandal, Debdeep Mukhopadhyay
Designing DPA Resistant Circuits Using BDD Architecture and Bottom Pre-charge Logic. DSD (2013)
Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal
Verification of KPN Level Transformations. VLSI Design (2013)
Chandan Karfa, Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal
Verification of Loop and Arithmetic Transformations of Array-Intensive Behaviors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (11) (2013)
Ariyam Das, Chittaranjan A. Mandal, Chris Reade
Determining the User Intent Behind Web Search Queries by Learning from Past User Interactions with Search Results. COMAD (2013)
Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
STAIRoute: Global routing using monotone staircase channels. ISVLSI (2013)
Bapi Kar, Susmita Sur-Kolay, Sridhar H. Rangarajan, Chittaranjan A. Mandal
A Faster Hierarchical Balanced Bipartitioner for VLSI Floorplans Using Monotone Staircase Cuts. VDAT (2012)
Priyankar Ghosh, Aritra Hazra, Rahul Gonnabhaktula, Niraj Bhilegaonkar, Pallab Dasgupta, Chittaranjan A. Mandal, Krishna Paul
POWER-SIM: An SOC Simulator for Estimating Power Profiles of Mobile Workloads. J. Low Power Electron. 8 (3) (2012)
Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar
Formal verification of code motion techniques using data-flow-driven equivalence checking. ACM Trans. Design Autom. Electr. Syst. 17 (3) (2012)
Arun Dobriyal, Rahul Gonnabattula, Pallab Dasgupta, Chittaranjan A. Mandal
Workload Driven Power Domain Partitioning. VDAT (2012)
Soumyadip Bandyopadhyay, Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal
Translation Validation for PRES+ Models of Parallel Behaviours via an FSMD Equivalence Checker. VDAT (2012)
Priyankar Ghosh, Aritra Hazra, Niraj Bhilegaonkar, Pallab Dasgupta, Chittaranjan A. Mandal, Krishna Paul
POWER-SIM: An SOC Simulator for Estimating Power Profiles of Mobile Workloads. ISED (2011)
Ariyam Das, Chittaranjan A. Mandal, Chris Reade, Manish Aasawat
An improved greedy construction of minimum connected dominating sets in wireless networks. WCNC (2011)
Soumya Pandit, Chittaranjan A. Mandal, Amit Patra
A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies. VLSI Design 2011 (2011)
Rajiv Misra, Chittaranjan A. Mandal
Minimum Connected Dominating Set Using a Collaborative Cover Heuristic for Ad Hoc Sensor Networks. IEEE Trans. Parallel Distributed Syst. 21 (3) (2010)
Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal
Data-Flow Driven Equivalence Checking for Verification of Code Motion Techniques. ISVLSI (2010)
Soumya Pandit, Chittaranjan A. Mandal, Amit Patra
An automated high-level topology generation procedure for continuous-time SigmaDelta modulator. Integr. 43 (3) (2010)
Gopal Paul, Santosh Biswas, Chittaranjan A. Mandal, Bhargab B. Bhattacharya
A BDD-based approach to design power-aware on-line detectors for digital circuits. SoCC (2010)
Gopal Paul, Rohit Reddy, Chittaranjan A. Mandal, Bhargab B. Bhattacharya
A BDD-Based Design of an Area-Power Efficient Asynchronous Adder. ISVLSI (2010)
Rajiv Misra, Chittaranjan A. Mandal
Rotation of CDS via Connected Domatic Partition in Ad Hoc Sensor Networks. IEEE Trans. Mob. Comput. 8 (4) (2009)
Rajiv Misra, Chittaranjan A. Mandal
domatic partition in self-organizing sensor networks. Wirel. Commun. Mob. Comput. 9 (8) (2009)
Soumya Pandit, Chittaranjan A. Mandal, Amit Patra
Systematic Methodology for High-Level Performance Modeling of Analog Systems. VLSI Design (2009)
Rajiv Misra, Chittaranjan A. Mandal
Location Updates of Mobile Node in Wireless Sensor Networks. MSN (2009)
Soumya Pandit, Sumit K. Bhattacharya, Chittaranjan A. Mandal, Amit Patra
A Fast Exploration Procedure for Analog High-Level Specification Translation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (8) (2008)
Rajiv Misra, Chittaranjan A. Mandal
ClusterHead Rotation via Domatic Partition in Self-Organizing Sensor Networks. COMSWARE (2007)
Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal, Chris Reade
Hand-in-hand verification of high-level synthesis. ACM Great Lakes Symposium on VLSI (2007)
Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, Chris Reade
Register Sharing Verification During Data-Path Synthesis. ICCTA (2007)
Vinay Vishwakarma, Chittaranjan A. Mandal, Shamik Sural
Automatic Detection of Human Fall in Video. PReMI (2007)
Amit Kumar Mandal, Chittaranjan A. Mandal, Chris Reade
A System for Automatic Evaluation of C Programs: Features and Interfaces. Int. J. Web Based Learn. Teach. Technol. 2 (4) (2007)
Chittaranjan A. Mandal, Chris Reade
Recipient Specific Electronic Cash - A Scheme for Recipient Specific Yet Anonymous and Tranferable Electronic Cash. WEBIST (3) (2007)
Soumya Pandit, Chittaranjan A. Mandal, Amit Patra
A formal approach for high level synthesis of linear analog systems. ACM Great Lakes Symposium on VLSI (2006)
Soumya Pandit, Sougata Kar, Chittaranjan A. Mandal, Amit Patra
High level synthesis of higher order continuous time state variable filters with minimum sensitivity and hardware count. DATE (2006)
Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade
Verification of Scheduling in High-level Synthesis. ISVLSI (2006)
Amit Kumar Mandal, Chittaranjan A. Mandal, Chris Reade
A System for Automatic Evaluation of Programs for Correctness and Performance. WEBIST (Selected Papers) (2006)
Amit Kumar Mandal, Chittaranjan A. Mandal, Chris Reade
A System for Automatic Evaluation of Programs for Correctness and Performance. WEBIST (2) (2006)
Chittaranjan A. Mandal, Chris Reade
Animating Algorithms over the Web. WEBIST (2) (2006)
Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade
A Formal Verification Method of Scheduling in High-level Synthesis. ISQED (2006)
Arijit Mondal, P. P. Chakrabarti, Chittaranjan A. Mandal
A New Approach to Timing Analysis Using Event Propagation and Temporal Logic. DATE (2004)
Bipin Rajendran, Veerbhan Kheterpal, Abhishek Das, Jayanta Majumder, Chittaranjan A. Mandal, P. P. Chakrabarti
Timing analysis of tree-like RLC circuits. ISCAS (4) (2002)
Chittaranjan A. Mandal, R. M. Zimmer
A Genetic Algorithm for the Synthesis of Structured Data Paths. VLSI Design (2000)
Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose
GABIND: a GA approach to allocation and binding for the high-level synthesis of data paths. IEEE Trans. Very Large Scale Integr. Syst. 8 (6) (2000)
Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose
A design space exploration scheme for data-path synthesis. IEEE Trans. Very Large Scale Integr. Syst. 7 (3) (1999)
Chittaranjan A. Mandal, Partha Pratim Chakrabarti, Sujoy Ghose
Complexity of Scheduling in High Level Synthesis. VLSI Design 1998 (4) (1998)
Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose
Design Space Exploration for Data Path Synthesis. VLSI Design (1997)
Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose
Allocation and Binding in Data Path Synthesis Using a Genetic Algorithm Approach. VLSI Design (1996)
Chittaranjan A. Mandal, Partha Pratim Chakrabarti, Sujoy Ghose
Interconnect Optimization Techniques in Data Path Synthesis. VLSI Design (1992)
Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose
Register-interconnect optimization in data path synthesis. Microprocess. Microprogramming 33 (5) (1992)