Dipankar Sarkar

Publication Activity (10 Years)

Years Active: 1989-2022
Publications (10 Years): 14

Top Topics

Causal Relations

High Level Synthesis

Embedded Systems

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal, Holger Giese
Translation validation of coloured Petri net models of programs on integers. Acta Informatica 59 (6) (2022)
Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan Mandal
Equivalence checking of Petri net models of programs using static and dynamic cut-points. Acta Informatica 56 (4) (2019)
Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan Mandal
SamaTulyataOne: A Path Based Equivalence Checker. ISEC (2019)
Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal
Verification of parallelising transformations of KPN models. IET Cyper-Phys. Syst.: Theory & Appl. 4 (3) (2019)
Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar
An Equivalence Checking Framework for Array-Intensive Programs. ATVA (2017)
Sudakshina Dutta, Dipankar Sarkar, Arvind Rawat
Synchronization Validation for Cross-Thread Dependences in Parallel Programs. Int. J. Parallel Program. 45 (6) (2017)
Kunal Banerjee, Dipankar Sarkar, Chittaranjan Mandal
Deriving Bisimulation Relations from Path Extension Based Equivalence Checkers. IEEE Trans. Software Eng. 43 (10) (2017)
Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal
Deriving bisimulation relations from path based equivalence checkers. Formal Aspects Comput. 29 (2) (2017)
Soumyadip Bandyopadhyay, Santonu Sarkar, Dipankar Sarkar, Chittaranjan A. Mandal
SamaTulyata: An Efficient Path Based Equivalence Checking Tool. ATVA (2017)
Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar
Translation validation of loop and arithmetic transformations in the presence of recurrences. LCTES (2016)
Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal
An efficient path based equivalence checking for Petri net based models of programs. ISEC (2016)
Sudakshina Dutta, Dipankar Sarkar, Arvind Rawat, Kulwant Singh
Validation of Loop Parallelization and Loop Vectorization Transformations. ENASE (2016)
Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal, Kunal Banerjee, Krishnam Raju Duddu
A Path Construction Algorithm for Translation Validation Using PRES+ Models. Parallel Process. Lett. 26 (2) (2016)
Sudakshina Dutta, Dipankar Sarkar
An Enhanced Equivalence Checking Method to Handle Bugs in Programs with Recurrences. ENASE (2016)
Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar
A translation validation framework for symbolic value propagation based equivalence checking of FSMDAs. SCAM (2015)
Soumyadip Bandyopadhyay, Dipankar Sarkar, Kunal Banerjee, Chittaranjan A. Mandal
A Path-based Equivalence Checking Method for Petri Net based Models of Programs. ICSOFT-EA (2015)
Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal
Validating SPARK: High Level Synthesis Compiler. ISVLSI (2015)
Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar
Translation Validation of Transformations of Embedded System Specifications Using Equivalence Checking. ISVLSI (2015)
Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal
Poster: An Efficient Equivalence Checking Method for Petri Net Based Models of Programs. ICSE (2) (2015)
Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar
Extending the scope of translation validation by augmenting path based equivalence checkers with SMT solvers. VDAT (2014)
Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal
Extending the FSMD Framework for Validating Code Motions of Array-Handling Programs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (12) (2014)
Kunal Banerjee, Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal
Verification of Code Motion Techniques Using Value Propagation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (8) (2014)
Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal
Verification of KPN Level Transformations. VLSI Design (2013)
Chandan Karfa, Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal
Verification of Loop and Arithmetic Transformations of Array-Intensive Behaviors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (11) (2013)
Soumyajit Dey, Dipankar Sarkar, Anupam Basu
A Kleene Algebra of Tagged System Actors for Reasoning about Heterogeneous Embedded Systems. IEEE Trans. Computers 62 (10) (2013)
Kunal Banerjee, Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal
A Value Propagation Based Equivalence Checking Method for Verification of Code Motion Techniques. ISED (2012)
Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar
Formal verification of code motion techniques using data-flow-driven equivalence checking. ACM Trans. Design Autom. Electr. Syst. 17 (3) (2012)
Soumyadip Bandyopadhyay, Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal
Translation Validation for PRES+ Models of Parallel Behaviours via an FSMD Equivalence Checker. VDAT (2012)
Chandan Karfa, Kunal Banerjee, Dipankar Sarkar, Chitta Mandal
Equivalence Checking of Array-Intensive Programs. ISVLSI (2011)
Chandan Karfa, Chitta Mandal, Dipankar Sarkar
Verification of Register Transfer Level Low Power Transformations. ISVLSI (2011)
Soumyajit Dey, Dipankar Sarkar, Anupam Basu
A Kleene Algebra of Tagged System Actors. IEEE Embed. Syst. Lett. 3 (1) (2011)
Santosh Biswas, Dipankar Sarkar, Siddhartha Mukhopadhyay, Amit Patra
Fairness of Transitions in Diagnosability of Discrete Event Systems. Discret. Event Dyn. Syst. 20 (3) (2010)
Santosh Biswas, Dipankar Sarkar, Siddhartha Mukhopadhyay
Diagnosability of delay-deadline failures in fair real time discrete event models. Int. J. Syst. Sci. 41 (7) (2010)
Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal
Data-Flow Driven Equivalence Checking for Verification of Code Motion Techniques. ISVLSI (2010)
Chandan Karfa, Dipankar Sarkar, Chitta Mandal
Verification of Datapath and Controller Generation Phase in High-Level Synthesis of Digital Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (3) (2010)
Soumyajit Dey, Dipankar Sarkar, Anupam Basu
A Tag Machine Based Performance Evaluation Method for Job-Shop Schedules. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (7) (2010)
Santosh Biswas, Siddhartha Mukhopadhyay, Amit Patra, Dipankar Sarkar
Unified Technique for on-Line Testing of Digital Circuits: Delay and Stuck-at Fault Models. J. Circuits Syst. Comput. 17 (6) (2008)
Chandan Karfa, Dipankar Sarkar, Chitta Mandal, P. Kumar
An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (3) (2008)
Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal, Chris Reade
Hand-in-hand verification of high-level synthesis. ACM Great Lakes Symposium on VLSI (2007)
Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, Chris Reade
Register Sharing Verification During Data-Path Synthesis. ICCTA (2007)
Prodip Bhowal, Dipankar Sarkar, Siddhartha Mukhopadhyay, Anupam Basu
Fault diagnosis in discrete time hybrid systems - A case study. Inf. Sci. 177 (5) (2007)
Santosh Biswas, Siddhartha Mukhopadhyay, P. Patra, Dipankar Sarkar
Concurrent Testing of Digital Circuits for Advanced Fault Models. DDECS (2006)
Santosh Biswas, Chandan Karfa, Himani Kanwar, Dipankar Sarkar, Siddhartha Mukhopadhyay, Amit Patra
Fairness of transitions in diagnosability analysis of hybrid systems. ACC (2006)
Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade
Verification of Scheduling in High-level Synthesis. ISVLSI (2006)
Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade
A Formal Verification Method of Scheduling in High-level Synthesis. ISQED (2006)
Santosh Biswas, P. Srikanth, R. Jha, Siddhartha Mukhopadhyay, Amit Patra, Dipankar Sarkar
On-Line Testing of Digital Circuits for n-Detect and Bridging Fault Models. Asian Test Symposium (2005)
Batsayan Das, Dipankar Sarkar, Santanu Chattopadhyay
Model checking on state transition diagram. ASP-DAC (2004)
Dipankar Sarkar
Register Transfer Operation Analysis during Data Path Verification. VLSI Design (2002)
Dipankar Sarkar
Status Condition Analysis during Data Path Verification of Sequential Circuits. VLSI Design (2000)
M. Hira, Dipankar Sarkar
Verification of Tempura specification of sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (4) (1997)
I. Chakrabarti, Dipankar Sarkar, Arun K. Majumdar
Inductive Verification of Sequential Circuits with a Datapath. VLSI Design (1997)
I. Chakrabarti, Dipankar Sarkar, Arun K. Majumdar
Identification of Inductive Properties during Verification of Synchronous Sequential Circuits. J. Autom. Reason. 14 (3) (1995)
I. Chakrabarti, Dipankar Sarkar
Mechanical Identification of Inductive Properties During Verification of Finite State Machines. VLSI Design (1994)
Dipankar Sarkar, S. C. De Sarkar
A Theorem Prover for Verifying Iterative Programs Over Integers. IEEE Trans. Software Eng. 15 (12) (1989)
Dipankar Sarkar, S. C. De Sarkar
A Set of Inference Rules for Quantified Formula Handling and Array Handling in Verification of Programs Over Integers. IEEE Trans. Software Eng. 15 (11) (1989)
Dipankar Sarkar, S. C. De Sarkar
Some Inference Rules for Integer Arithmetic for Verification of Flowchart Programs on Integers. IEEE Trans. Software Eng. 15 (1) (1989)