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Verification of Datapath and Controller Generation Phase in High-Level Synthesis of Digital Circuits.
Chandan Karfa
Dipankar Sarkar
Chitta Mandal
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2010)
Keyphrases
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digital circuits
high level synthesis
data flow
model checking
model based diagnosis
finite state machines
parallel architecture
control system
pattern recognition
circuit design
database
probabilistic model
design space exploration
functional decomposition
hardware implementation
decision diagrams