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An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis.
Chandan Karfa
Dipankar Sarkar
Chitta Mandal
P. Kumar
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2008)
Keyphrases
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high accuracy
artificial intelligence
preprocessing
significant improvement
dynamic programming
scheduling problem
clustering method
feature selection
case study
similarity measure
support vector machine
signal processing
detection method