Model checking on state transition diagram.
Batsayan DasDipankar SarkarSantanu ChattopadhyayPublished in: ASP-DAC (2004)
Keyphrases
- model checking
- temporal logic
- formal specification
- formal verification
- model checker
- finite state
- temporal properties
- partial order reduction
- process algebra
- automated verification
- formal methods
- finite state machines
- epistemic logic
- reachability analysis
- transition systems
- timed automata
- pspace complete
- computation tree logic
- concurrent systems
- symbolic model checking
- bounded model checking
- verification method
- asynchronous circuits
- satisfiability problem
- artificial intelligence
- ordered binary decision diagrams
- deterministic finite automaton
- planning domains