A Formal Verification Method of Scheduling in High-level Synthesis.
Chandan KarfaChittaranjan A. MandalDipankar SarkarS. R. PentakotaChris ReadePublished in: ISQED (2006)
Keyphrases
- verification method
- high level synthesis
- model checking
- temporal logic
- formal specification
- formal methods
- scheduling algorithm
- scheduling problem
- parallel architecture
- round robin
- parallel machines
- resource constraints
- pairwise
- probabilistic model
- search space
- message passing
- expert systems
- parallel algorithm
- user interface
- computer systems
- response time