Login / Signup
Partha De
ORCID
Publication Activity (10 Years)
Years Active: 2013-2020
Publications (10 Years): 3
Top Topics
Classical Logic
Power Analysis
Hardware Design
Countermeasures
Top Venues
DSD
WiOpt
IEEE Trans. Circuits Syst.
IEEE Trans. Very Large Scale Integr. Syst.
</>
Publications
</>
Partha De
,
Udaya Parampalli
,
Chittaranjan Mandal
Secure Path Balanced BDD-Based Pre-Charge Logic for Masking.
IEEE Trans. Circuits Syst.
(12) (2020)
Partha De
,
Chittaranjan Mandal
,
Udaya Parampalli
Path-Balanced Logic Design to Realize Block Ciphers Resistant to Power and Timing Attacks.
IEEE Trans. Very Large Scale Integr. Syst.
27 (5) (2019)
Partha De
,
Kamil Saraç
,
Ramaswamy Chandrasekaran
Heuristics for 2-coverage multi point relay problem in wireless ad hoc and sensor networks.
WiOpt
(2016)
Partha De
,
Kunal Banerjee
,
Chittaranjan A. Mandal
,
Debdeep Mukhopadhyay
Circuits and Synthesis Mechanism for Hardware Design to Counter Power Analysis Attacks.
DSD
(2014)
Partha De
,
Kunal Banerjee
,
Chittaranjan A. Mandal
A BDD based secure hardware design method to guard against power analysis attacks.
VDAT
(2014)
Partha De
,
Kunal Banerjee
,
Chittaranjan A. Mandal
,
Debdeep Mukhopadhyay
Designing DPA Resistant Circuits Using BDD Architecture and Bottom Pre-charge Logic.
DSD
(2013)