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A Faster Hierarchical Balanced Bipartitioner for VLSI Floorplans Using Monotone Staircase Cuts.
Bapi Kar
Susmita Sur-Kolay
Sridhar H. Rangarajan
Chittaranjan A. Mandal
Published in:
VDAT (2012)
Keyphrases
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high speed
upper bound
coarse to fine
total variation
vlsi design
vlsi circuits
real time
image processing
hierarchical structure
hierarchical clustering
highly efficient
hierarchical classification
memory efficient
hierarchical representation