Susmita Sur-Kolay

ORCID

Publication Activity (10 Years)

Years Active: 1988-2024
Publications (10 Years): 52

Top Venues

CoRR

VLSI Design

IEEE Trans. Very Large Scale Integr. Syst.

ISVLSI

Publications

Mukta Debnath, Animesh Basak Chowdhury, Debasri Saha, Susmita Sur-Kolay
Scalable Test Generation to Trigger Rare Targets in High-Level Synthesizable IPs for Cloud FPGAs. CoRR (2024)
Ritajit Majumdar, Dhiraj Madan, Debasmita Bhoumik, Dhinakaran Vinayagamurthy, Shesha Raghunathan, Susmita Sur-Kolay
Optimized QAOA ansatz circuit design for two-body Hamiltonian problems. VLSID (2024)
Debasmita Bhoumik, Ritajit Majumdar, Susmita Sur-Kolay
Resource-aware scheduling of multiple quantum circuits on a hardware device. CoRR (2024)
Ritajit Majumdar, Amit Saha, Amlan Chakrabarti, Susmita Sur-Kolay
Intermediate qutrit-assisted Toffoli gate decomposition with quantum error correction. Quantum Inf. Process. 23 (2) (2024)
Rikathi Pal, Priya Saha, Somoballi Ghoshal, Amlan Chakrabarti, Susmita Sur-Kolay
Panoptic Segmentation and Labelling of Lumbar Spine Vertebrae using Modified Attention Unet. CoRR (2024)
Rikathi Pal, Sudeshna Mondal, Aditi Gupta, Priya Saha, Somoballi Ghoshal, Amlan Chakrabarti, Susmita Sur-Kolay
Lumbar Spine Tumor Segmentation and Localization in T2 MRI Images Using AI. CoRR (2024)
Saikat Basu, Arnav Das, Amit Saha, Amlan Chakrabarti, Susmita Sur-Kolay
FragQC: An efficient quantum error reduction technique using quantum circuit fragmentation. J. Syst. Softw. 214 (2024)
Archan Ghosh, Debgandhar Ghosh, Somoballi Ghoshal, Amlan Chakrabarti, Susmita Sur-Kolay
Segmentation and Labeling of Vertebra Using SegFormer Architecture. CVIP (2) (2023)
Saikat Basu, Arnav Das, Amit Saha, Amlan Chakrabarti, Susmita Sur-Kolay
FragQC: An Efficient Quantum Error Reduction Technique using Quantum Circuit Fragmentation. CoRR (2023)
Manobendra Nath Mondal, Susmita Sur-Kolay, Bhargab B. Bhattacharya
Test Optimization in Memristor Crossbars Based on Path Selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (1) (2023)
Sudipta Paul, Tridib Mukherjee, Pritha Banerjee, Susmita Sur-Kolay
Concurrent Steiner Tree Selection for Global routing with EUVL Flare Reduction. Integr. 92 (2023)
Somoballi Ghoshal, Shremoyee Goswami, Amlan Chakrabarti, Susmita Sur-Kolay
Fast 3D Volumetric Image Reconstruction from 2D MRI Slices by Parallel Processing. CoRR (2023)
Ritajit Majumdar, Susmita Sur-Kolay
Designing Ternary Quantum Error Correcting Codes from Binary Codes. J. Multiple Valued Log. Soft Comput. 40 (1-2) (2023)
Mukta Debnath, Krishnendu Guha, Debasri Saha, Susmita Sur-Kolay
AgEncID: Aggregate Encryption Individual Decryption of Key for FPGA Bitstream IP Cores in Cloud. CoRR (2023)
Mukta Debnath, Animesh Basak Chowdhury, Debasri Saha, Susmita Sur-Kolay
GreyConE: Greybox Fuzzing + Concolic Execution Guided Test Generation for High Level Designs. ITC (2022)
Amit Saha, Ritajit Majumdar, Debasri Saha, Amlan Chakrabarti, Susmita Sur-Kolay
Faster search of clustered marked states with lackadaisical quantum walks. Quantum Inf. Process. 21 (8) (2022)
Debasmita Bhoumik, Ritajit Majumdar, Dhiraj Madan, Dhinakaran Vinayagamurthy, Shesha Raghunathan, Susmita Sur-Kolay
Efficient Machine-Learning-based decoder for Heavy Hexagonal QECC. CoRR (2022)
Kritanta Saha, Pritha Banerjee, Susmita Sur-Kolay
Stitch-avoiding Detailed Routing for Multiple E-Beam Lithography. VLSI-SoC (2022)
Mukta Debnath, Animesh Basak Chowdhury, Debasri Saha, Susmita Sur-Kolay
Test Generation for SystemC designs by interlaced Greybox Fuzzing and Concolic Execution. CoRR (2022)
Santlal Prajaprati, Manobendra Nath Mondal, Susmita Sur-Kolay
Memristive Neural Network with Efficient In-Situ Supervised Training. SOCC (2022)
Kritanta Saha, Sudipta Paul, Pritha Banerjee, Susmita Sur-Kolay
Stitch-avoiding Global Routing for Multiple E-Beam Lithography. VLSID (2022)
Mukta Debnath, Animesh Basak Chowdhury, Debasri Saha, Susmita Sur-Kolay
FuCE: Fuzzing+Concolic Execution guided Trojan Detection in Synthesizable Hardware Designs. CoRR (2021)
Debasri Saha, Susmita Sur-Kolay
Minimization of WCRT with Recovery Assurance from Hardware Trojans for Tasks on FPGA-based Cloud. ACM Trans. Embed. Comput. Syst. 20 (1) (2021)
Sudipta Paul, Pritha Banerjee, Susmita Sur-Kolay
A study on flare minimisation in EUV lithography by post-layout re-allocation of wire segments. IET Circuits Devices Syst. 15 (4) (2021)
Somoballi Ghoshal, Partha Bhowmick, Amlan Chakrabarti, Susmita Sur-Kolay, Sanjukta Chakravorti, Dhurjati Sengupta
3D Reconstruction from Micro-CT Slices for Non-Destructive Viewing inside a Fossil. IVCNZ (2021)
Ritajit Majumdar, Debasmita Bhoumik, Dhiraj Madan, Dhinakaran Vinayagamurthy, Shesha Raghunathan, Susmita Sur-Kolay
Depth Optimized Ansatz Circuit in QAOA for Max-Cut. CoRR (2021)
Ritajit Majumdar, Dhiraj Madan, Debasmita Bhoumik, Dhinakaran Vinayagamurthy, Shesha Raghunathan, Susmita Sur-Kolay
Optimizing Ansatz Design in QAOA for Max-cut. CoRR (2021)
Manobendra Nath Mondal, Susmita Sur-Kolay, Bhargab B. Bhattacharya
Current Comparator-Based Reconfigurable Adder and Multiplier on Hybrid Memristive Crossbar. ISVLSI (2020)
Ritajit Majumdar, Susmita Sur-Kolay
Approximate Ternary Quantum Error Correcting Code with Low Circuit Cost. ISMVL (2020)
Ritajit Majumdar, Susmita Sur-Kolay
Special Session: Quantum Error Correction in Near Term Systems. ICCD (2020)
Somoballi Ghoshal, Sourav Banu, Amlan Chakrabarti, Susmita Sur-Kolay, Alok Pandit
3D reconstruction of spine image from 2D MRI slices along one axis. IET Image Process. 14 (12) (2020)
Ritajit Majumdar, Susmita Sur-Kolay
Exploiting degeneracy to construct good ternary quantum error correcting code. CoRR (2020)
Amit Saha, Ritajit Majumdar, Debasri Saha, Amlan Chakrabarti, Susmita Sur-Kolay
Asymptotically Improved Grover's Algorithm in any Dimensional Quantum System with Novel Decomposed n-qudit Toffoli Gate. CoRR (2020)
Sudipta Paul, Pritha Banerjee, Susmita Sur-Kolay
Minimization of Flare in EUVL by Simultaneous Wire Segment Perturbation and Dummification. ISVLSI (2019)
Manobennath Mondal, Susmita Sur-Kolay, Bhargab B. Bhattacharya
Selective Sensitization of Useless Sneak-Paths for Test Optimization in Memristor-Arrays. VLSI Design (2019)
Manobendra Nath Mondal, Animesh Basak Chowdhury, Manjari Pradhan, Susmita Sur-Kolay, Bhargab B. Bhattacharya
Fault Coverage of a Test Set on Structure-Preserving Siblings of a Circuit-Under-Test. ATS (2019)
Debasri Saha, Susmita Sur-Kolay
Guided GA-Based Multiobjective Optimization of Placement and Assignment of TSVs in 3-D ICs. IEEE Trans. Very Large Scale Integr. Syst. 27 (8) (2019)
Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
Exploring the Scope of Unconstrained Via Minimization by Recursive Floorplan Bipartitioning. CoRR (2018)
Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
STAIRoute: Early Global Routing using Monotone Staircases for Congestion Reduction. CoRR (2018)
Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
Early Routability Assessment in VLSI Floorplans: A Generalized Routing Model. CoRR (2018)
Arsalan Mosenia, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha
Wearable Medical Sensor-Based System Design: A Survey. IEEE Trans. Multi Scale Comput. Syst. 3 (2) (2017)
Debasri Saha, Susmita Sur-Kolay
Multi-objective Optimization of Placement and Assignment of TSVs in 3D ICs. VLSI Design (2017)
Arsalan Mosenia, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha
DISASTER: Dedicated Intelligent Security Attacks on Sensor-Triggered Emergency Responses. IEEE Trans. Multi Scale Comput. Syst. 3 (4) (2017)
Ritajit Majumdar, Saikat Basu, Susmita Sur-Kolay
A Method to Reduce Resources for Quantum Error Correction. RC (2017)
Sudipta Paul, Pritha Banerjee, Susmita Sur-Kolay
Post-Layout Perturbation towards Stitch Friendly Layout for Multiple E-Beam Lithography. ICCD (2017)
Arsalan Mosenia, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha
CABA: Continuous Authentication Based on BioAura. IEEE Trans. Computers 66 (5) (2017)
Debasri Saha, Susmita Sur-Kolay
Embedding of signatures in reconfigurable scan architecture for authentication of intellectual properties in system-on-chip. IET Comput. Digit. Tech. 10 (3) (2016)
Arsalan Mohsen Nia, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha
Physiological Information Leakage: A New Frontier in Health Information Security. IEEE Trans. Emerg. Top. Comput. 4 (3) (2016)
Saikat Basu, Sudhindu Bikash Mandal, Amlan Chakrabarti, Susmita Sur-Kolay
An efficient synthesis method for ternary reversible logic. ISCAS (2016)
Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
A Novel EPE Aware Hybrid Global Route Planner after Floorplanning. VLSI Design (2016)
Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
An early global routing framework for uniform wire distribution in SoCs. SoCC (2016)
Ritajit Majumdar, Saikat Basu, Priyanka Mukhopadhyay, Susmita Sur-Kolay
Error tracing in linear and concatenated quantum circuits. CoRR (2016)
Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
A New Method for Defining Monotone Staircases in VLSI Floorplans. ISVLSI (2015)
Chia-Chun Lin, Susmita Sur-Kolay, Niraj K. Jha
PAQCS: Physical Design-Aware Fault-Tolerant Quantum Circuit Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 23 (7) (2015)
Sudhindu Bikash Mandal, Amlan Chakrabarti, Susmita Sur-Kolay
Quantum Ternary Circuit Synthesis Using Projection Operations. J. Multiple Valued Log. Soft Comput. 24 (1-4) (2015)
Mehran Mozaffari Kermani, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha
Systematic Poisoning Attacks on and Defenses for Machine Learning in Healthcare. IEEE J. Biomed. Health Informatics 19 (6) (2015)
Arsalan Mohsen Nia, Mehran Mozaffari Kermani, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha
Energy-Efficient Long-term Continuous Personal Health Monitoring. IEEE Trans. Multi Scale Comput. Syst. 1 (2) (2015)
Gautam K. Das, Minati De, Sudeshna Kolay, Subhas C. Nandy, Susmita Sur-Kolay
Approximation algorithms for maximum independent set of a unit disk graph. Inf. Process. Lett. 115 (3) (2015)
Sudipta Paul, Pritha Banerjee, Susmita Sur-Kolay
Flare reduction in EUV Lithography by perturbation of wire segments. VLSI-SoC (2015)
Debasri Saha, Susmita Sur-Kolay
Watermarking in Hard Intellectual Property for Pre-Fab and Post-Fab Verification. IEEE Trans. Very Large Scale Integr. Syst. 23 (5) (2015)
Debasri Saha, Susmita Sur-Kolay
Trusted sharing of intellectual property in electronic hardware design. WESS (2014)
Sumit Saha, Bapi Kar, Susmita Sur-Kolay
A novel architecture for QPSK modulation based on time-mode signal processing. VDAT (2014)
Arighna Deb, Debesh Kumar Das, Susmita Sur-Kolay
A Modular Design to Synthesize Symmetric Functions Using Quantum Quaternary Logic. J. Low Power Electron. 10 (3) (2014)
Arani Bhattacharya, Ansuman Banerjee, Susmita Sur-Kolay
Energy-Aware H.264 Decoding. ICDCIT (2014)
Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
Global Routing Using Monotone Staircases with Minimal Bends. VLSI Design (2014)
Sudhindu Bikash Mandal, Amlan Chakrabarti, Susmita Sur-Kolay
Synthesis of Ternary Grover's Algorithm. ISMVL (2014)
Arighna Deb, Debesh K. Das, Susmita Sur-Kolay
Modular Design for Symmetric Functions Using Quantum Quaternary Logic. ISED (2013)
Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal
STAIRoute: Global routing using monotone staircase channels. ISVLSI (2013)
Arani Bhattacharya, Ansuman Banerjee, Susmita Sur-Kolay, Prasenjit Basu, Bhaskar J. Karmakar
A Cache-Aware Strategy for H.264 Decoding on Multi-processor Architectures. VDAT (2013)
Bapi Kar, Susmita Sur-Kolay, Sridhar H. Rangarajan, Chittaranjan A. Mandal
A Faster Hierarchical Balanced Bipartitioner for VLSI Floorplans Using Monotone Staircase Cuts. VDAT (2012)
Sudhindu Bikash Mandal, Amlan Chakrabarti, Susmita Sur-Kolay
A Synthesis Method for Quaternary Quantum Logic Circuits. VDAT (2012)
Susmita Sur-Kolay, Swarup Bhunia
Tutorial T4: Intellectual Property Protection and Security in System-on-Chip Design. VLSI Design (2012)
Debasri Saha, Susmita Sur-Kolay
Secure Public Verification of IP Marks in FPGA Design Through a Zero-Knowledge Protocol. IEEE Trans. Very Large Scale Integr. Syst. 20 (10) (2012)
Sudhindu Bikash Mandal, Amlan Chakrabarti, Susmita Sur-Kolay
A Synthesis Method for Quaternary Quantum Logic Circuits CoRR (2012)
Susmita Sur-Kolay
Intellectual property protection and security of SoCs - An embedded tutorial. SoCC (2012)
Amlan Chakrabarti, Susmita Sur-Kolay, Ayan Chaudhury
Linear Nearest Neighbor Synthesis of Reversible Circuits by Graph Partitioning CoRR (2011)
Pritha Banerjee, Debasri Saha, Susmita Sur-Kolay
Cone-based placement for field programmable gate arrays. IET Comput. Digit. Tech. 5 (1) (2011)
Ayan Datta, Charudhattan Nagarajan, Susmita Sur-Kolay
TSV-aware Scan Chain Reordering for 3D IC. ISVLSI (2011)
Debasri Saha, Susmita Sur-Kolay
SoC: A Real Platform for IP Reuse, IP Infringement, and IP Protection. VLSI Design 2011 (2011)
Pritha Banerjee, Megha Sangtani, Susmita Sur-Kolay
Floorplanning for Partially Reconfigurable FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (1) (2011)
Sudhindu Bikash Mandal, Amlan Chakrabarti, Susmita Sur-Kolay
Synthesis Techniques for Ternary Quantum Logic. ISMVL (2011)
Debasri Saha, Susmita Sur-Kolay
Robust intellectual property protection of VLSI physical design. IET Comput. Digit. Tech. 4 (5) (2010)
Debasri Saha, Susmita Sur-Kolay
A Unified Approach for IP Protection across Design Phases in a Packaged Chip. VLSI Design (2010)
Debasis Mitra, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Sandip Kundu, Ashish Nigam, Sandeep K. Dey
Test pattern generation for droop faults. IET Comput. Digit. Tech. 4 (4) (2010)
Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu, Sandip Das, Subhas C. Nandy, Subhasis Bhattacharjee
FPGA placement using space-filling curves: Theory meets practice. ACM Trans. Embed. Comput. Syst. 9 (2) (2009)
Debasis Mitra, Susmita Sur-Kolay, Bhargab B. Bhattacharya
Droop sensitivity of stuck-at fault tests. IET Comput. Digit. Tech. 3 (2) (2009)
Susmita Sur-Kolay, Satyajit Banerjee, S. Mukhopadhyaya, C. A. Murthy
The Double Digest Problem: finding all solutions. Int. J. Bioinform. Res. Appl. 5 (5) (2009)
Debasri Saha, Susmita Sur-Kolay
Encoding of Floorplans through Deterministic Perturbation. VLSI Design (2009)
Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu
Fast Unified Floorplan Topology Generation and Sizing on Heterogeneous FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (5) (2009)
Sriparna Saha, Susmita Sur-Kolay, Parthasarathi Dasgupta, Sanghamitra Bandyopadhyay
MAkE: Multiobjective algorithm for k-way equipartitioning of a point set. Appl. Soft Comput. 9 (2) (2009)
Debasri Saha, Susmita Sur-Kolay
Secure Leakage-Proof Public Verification of IP Marks in VLSI Physical Design. ISVLSI (2009)
Pritha Banerjee, Megha Sangtani, Susmita Sur-Kolay
Floorplanning for Partial Reconfiguration in FPGAs. VLSI Design (2009)
Debasri Saha, Susmita Sur-Kolay
An Analytical Approach to Direct IP Protection of VLSI Floorplans. ICIIS (2008)
Debasri Saha, Parthasarathi Dasgupta, Susmita Sur-Kolay, Samar Sen-Sarma
A Novel Scheme for Encoding and Watermark Embedding in VLSI Physical Design for IP Protection. ICCTA (2007)
Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu
Floorplanning in Modern FPGAs. VLSI Design (2007)
Amlan Chakrabarti, Susmita Sur-Kolay
Nearest Neighbour based Synthesis of Quantum Boolean Circuits. Eng. Lett. 15 (2) (2007)
Pritha Banerjee, Susmita Sur-Kolay
Faster Placer for Island-Style FPGAs. ICCTA (2007)
Debasri Saha, Susmita Sur-Kolay
Fast Robust Intellectual Property Protection for VLSI Physical Design. ICIT (2007)
Subhashis Majumder, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Swarup Kumar Das
Hierarchical partitioning of VLSI floorplans by staircases. ACM Trans. Design Autom. Electr. Syst. 12 (1) (2007)
Sriparna Saha, Susmita Sur-Kolay, Sanghamitra Bandyopadhyay, Parthasarathi Dasgupta
Multiobjective Genetic Algorithm for k-way Equipartitioning of a Point Set with Application to CAD-VLSI. ICIT (2006)

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Publication Activity (10 Years)

Top Topics

Top Venues

Susmita Sur-Kolay