Pritha Banerjee

Publication Activity (10 Years)

Years Active: 2005-2022
Publications (10 Years): 8

Top Topics

Top Venues

Microelectron. J.

IET Circuits Devices Syst.

Publications

Pritha Banerjee, Jayoti Das
Threshold voltage modeling of Gaussian-doped Dual work function Material Cylindrical Gate-all-around (CGAA) MOSFET considering the effect of temperature and fixed interface trapped charges. Microelectron. J. 120 (2022)
Kritanta Saha, Pritha Banerjee, Susmita Sur-Kolay
Stitch-avoiding Detailed Routing for Multiple E-Beam Lithography. VLSI-SoC (2022)
Kritanta Saha, Sudipta Paul, Pritha Banerjee, Susmita Sur-Kolay
Stitch-avoiding Global Routing for Multiple E-Beam Lithography. VLSID (2022)
Sudipta Paul, Pritha Banerjee, Susmita Sur-Kolay
A study on flare minimisation in EUV lithography by post-layout re-allocation of wire segments. IET Circuits Devices Syst. 15 (4) (2021)
Sudipta Paul, Pritha Banerjee, Susmita Sur-Kolay
Minimization of Flare in EUVL by Simultaneous Wire Segment Perturbation and Dummification. ISVLSI (2019)
Pritha Banerjee, Priyanka Saha, Subir Kumar Sarkar
Analytical modelling and performance analysis of gate engineered TG silicon-on-nothing metal-oxide-semiconductor field-effect transistor. IET Circuits Devices Syst. 12 (5) (2018)
Sudipta Paul, Pritha Banerjee, Susmita Sur-Kolay
Post-Layout Perturbation towards Stitch Friendly Layout for Multiple E-Beam Lithography. ICCD (2017)
Pritha Banerjee, Anup Sarkar, Subir Kumar Sarkar
Exploring the short channel characteristics and performance analysis of DMDG SON MOSFET. Microelectron. J. 67 (2017)
Sudipta Paul, Pritha Banerjee, Susmita Sur-Kolay
Flare reduction in EUV Lithography by perturbation of wire segments. VLSI-SoC (2015)
Tzu-Hen Lin, Pritha Banerjee, Yao-Wen Chang
An efficient and effective analytical placer for FPGAs. DAC (2013)
Pritha Banerjee, Debasri Saha, Susmita Sur-Kolay
Cone-based placement for field programmable gate arrays. IET Comput. Digit. Tech. 5 (1) (2011)
Pritha Banerjee, Megha Sangtani, Susmita Sur-Kolay
Floorplanning for Partially Reconfigurable FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (1) (2011)
Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu, Sandip Das, Subhas C. Nandy, Subhasis Bhattacharjee
FPGA placement using space-filling curves: Theory meets practice. ACM Trans. Embed. Comput. Syst. 9 (2) (2009)
Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu
Fast Unified Floorplan Topology Generation and Sizing on Heterogeneous FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (5) (2009)
Pritha Banerjee, Megha Sangtani, Susmita Sur-Kolay
Floorplanning for Partial Reconfiguration in FPGAs. VLSI Design (2009)
Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu
Floorplanning in Modern FPGAs. VLSI Design (2007)
Pritha Banerjee, Susmita Sur-Kolay
Faster Placer for Island-Style FPGAs. ICCTA (2007)
Pritha Banerjee, Subhasis Bhattacharjee, Susmita Sur-Kolay, Sandip Das, Subhas C. Nandy
Fast FPGA Placement using Space-filling Curve. FPL (2005)