Secure Public Verification of IP Marks in FPGA Design Through a Zero-Knowledge Protocol.
Debasri SahaSusmita Sur-KolayPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2012)
Keyphrases
- design process
- cryptographic protocols
- knowledge based systems
- formal analysis
- knowledge management
- formal verification
- verilog hdl
- model checking
- end to end
- scalar product
- key exchange protocol
- hardware architecture
- security analysis
- functional verification
- covert channel
- group communication
- hardware design
- formal methods
- security issues
- hardware implementation
- high speed