Formal Verification of Optimizing Transformations during High-level Synthesis.

Ramanuj Chouksey Chandan Karfa Purandar Bhaduri

Published in: ISEC (2019)

Keyphrases

formal verification
high level synthesis
model checking
automated verification
model checker
bounded model checking
parallel architecture
symbolic model checking
program slicing
temporal logic
artificial intelligence
computer vision
np hard