Simultaneous Constrained Pin Assignment and Escape Routing Considering Differential Pairs for FPGA-PCB Co-Design.
Seong-I LeiWai-Kei MakPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2013)
Keyphrases
- pairwise
- low cost
- routing algorithm
- network topology
- hardware implementation
- defect detection
- shortest path
- ad hoc networks
- inter domain
- routing problem
- real time image processing
- hardware architecture
- network topologies
- printed circuit boards
- hardware design
- field programmable gate array
- systolic array
- routing protocol
- real time
- neural network
- dedicated hardware
- routing decisions
- verilog hdl
- traffic engineering
- wireless ad hoc networks
- mobile ad hoc networks
- computing systems
- end to end
- signal processing