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Binding Hardware IPs to Specific FPGA Device via Inter-twining the PUF Response with the FSM of Sequential Circuits.
Jiliang Zhang
Yaping Lin
Yongqiang Lu
Ray C. C. Cheung
Wenjie Che
Qiang Zhou
Jinian Bian
Published in:
FCCM (2013)
Keyphrases
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fpga device
hardware implementation
real time
hardware and software
field programmable gate array
low cost
finite state machines
digital circuits
high speed
circuit design
image segmentation
intra class
image processing
pattern recognition
object oriented
computing systems
massively parallel
information systems