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A New Methodology of Integrating High Level Synthesis and Floorplan for SoC Design.
Yunfeng Wang
Jinian Bian
Xianlong Hong
Liu Yang
Qiang Zhou
Qiang Wu
Published in:
ICESS (2005)
Keyphrases
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high level synthesis
design methodology
design process
user interface
low cost
hardware and software
information systems
computer aided
efficient implementation
parallel architecture