An FPGA Architecture to Accelerate the Burrows Wheeler Transform by Using a Linear Sorter.
Juan Andrés Pérez-CelisJosé Martínez-CarranzaAlicia Morales-ReyesClaudia Feregrino UribeRené CumplidoPublished in: IPDPS Workshops (2016)
Keyphrases
- hardware architecture
- hardware implementation
- real time
- hardware design
- management system
- parallel architecture
- dedicated hardware
- software implementation
- signal processing
- fpga technology
- real time image processing
- fpga implementation
- pipelined architecture
- field programmable gate array
- neural network
- fpga device
- network architecture
- data acquisition
- database
- low cost
- reconfigurable hardware
- hardware architectures
- systolic array