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A hardware architecture for filtering irreducible testors.
Vladimir Rodriguez
José F. Martínez
Jesús Ariel Carrasco-Ochoa
Manuel Sabino Lazo-Cortés
René Cumplido
Claudia Feregrino Uribe
Published in:
ReConFig (2014)
Keyphrases
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hardware architecture
hardware implementation
hardware architectures
associative memory
field programmable gate array
processing elements
neural network
image processing
information systems
scheduling problem
general purpose
efficient implementation
floating point