Run-time power and performance scaling with CPU-FPGA hybrids.

José L. Núñez-Yáñez Arash Beldachi

Published in: AHS (2014)

Keyphrases

power consumption
power reduction
multithreading
real time
field programmable gate array
hardware implementation
high speed
fpga implementation
data acquisition
signal processing
low cost
real time image processing
database
hardware architecture
digital signal processing
power distribution
digital signal