A Low-complexity FPGA TDC based on a DSP Delay Line and a Wave Union Launcher.
Zijie WangJiajun LuJosé L. Núñez-YáñezPublished in: DSD (2022)
Keyphrases
- low complexity
- verilog hdl
- digital signal processing
- systolic array
- real time image processing
- digital signal
- signal processing
- high speed
- field programmable gate array
- lower complexity
- motion estimation
- hardware implementation
- computational complexity
- low power
- distributed video coding
- wireless video
- bit plane
- video encoding
- high data rate
- image processing
- video processing
- video streaming
- machine learning
- power consumption
- video coding scheme