Mohammad Reza Kakoee

Publication Activity (10 Years)

Years Active: 2003-2015
Publications (10 Years): 1

Top Topics

Multi Processor

Shared Memory Multiprocessors

Ultra Low Power

Top Venues

IEEE Trans. Computers

Int. J. Embed. Real Time Commun. Syst.

IEEE Trans. Circuits Syst. I Regul. Pap.

Conf. Computing Frontiers

Publications

Masoud Dehyadegari, Andrea Marongiu, Mohammad Reza Kakoee, Siamak Mohammadi, Nasser Yazdani, Luca Benini
Architecture Support for Tightly-Coupled Multi-Core Clusters with Shared-Memory HW Accelerators. IEEE Trans. Computers 64 (8) (2015)
Mohammad Reza Kakoee, Valeria Bertacco, Luca Benini
At-Speed Distributed Functional Testing to Detect Logic and Delay Faults in NoCs. IEEE Trans. Computers 63 (3) (2014)
Mohammad Reza Kakoee, Igor Loi, Luca Benini
A shared-FPU architecture for ultra-low power MPSoCs. Conf. Computing Frontiers (2013)
Masoud Dehyadegari, Andrea Marongiu, Mohammad Reza Kakoee, Luca Benini, Siamak Mohammadi, Nasser Yazdani
A tightly-coupled multi-core cluster with shared-memory HW accelerators. ICSAMOS (2012)
Milos Krstic, Xin Fan, Eckhard Grass, Luca Benini, Mohammad Reza Kakoee, Christoph Heer, Birgit Sanders, Alessandro Strano, Davide Bertozzi
Evaluation of GALS Methods in Scaled CMOS Technology: Moonrake Chip Experience. Int. J. Embed. Real Time Commun. Syst. 3 (4) (2012)
Mohammad Reza Kakoee, Igor Loi, Luca Benini
A resilient architecture for low latency communication in shared-L1 processor clusters. DATE (2012)
Mohammad Reza Kakoee, Igor Loi, Luca Benini
Variation-Tolerant Architecture for Ultra Low Power Shared-L1 Processor Clusters. IEEE Trans. Circuits Syst. II Express Briefs (12) (2012)
Mohammad Reza Kakoee, Vladimir Petrovic, Luca Benini
A multi-banked shared-l1 cache architecture for tightly coupled processor clusters. ISSoC (2012)
Mohammad Reza Kakoee, Luca Benini
Robust Near-Threshold Design With Fine-Grained Performance Tunability. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2012)
Mohammad Reza Kakoee, Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini
Row-based FBB: A design-time optimization for post-silicon tunable circuits. Microelectron. J. 43 (7) (2012)
Milos Krstic, Xin Fan, Eckhard Grass, Christoph Heer, Birgit Sanders, Luca Benini, Mohammad Reza Kakoee, Alessandro Strano, Davide Bertozzi
Moonrake chip - GALS demonstrator in 40 nm CMOS technology. SoC (2011)
Mohammad Reza Kakoee, Valeria Bertacco, Luca Benini
A distributed and topology-agnostic approach for on-line NoC testing. NOCS (2011)
Mohammad Reza Kakoee, Luca Benini
Fine-Grained Power and Body-Bias Control for Near-Threshold Deep Sub-Micron CMOS Circuits. IEEE J. Emerg. Sel. Topics Circuits Syst. 1 (2) (2011)
Mohammad Reza Kakoee, Valeria Bertacco, Luca Benini
ReliNoC: A reliable network for priority-based on-chip communication. DATE (2011)
Abbas Rahimi, Igor Loi, Mohammad Reza Kakoee, Luca Benini
A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters. DATE (2011)
Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan
Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph. IEEE Trans. Very Large Scale Integr. Syst. 19 (8) (2011)
Mohammad Reza Kakoee, Igor Loi, Luca Benini
A new physical routing approach for robust bundled signaling on NoC links. ACM Great Lakes Symposium on VLSI (2010)
Mohammad Reza Kakoee, Ashoka Visweswara Sathanur, Antonio Pullini, Jos Huisken, Luca Benini
Automatic synthesis of near-threshold circuits with fine-grained performance tunability. ISLPED (2010)
Mohammad Reza Kakoee, Federico Angiolini, Srinivasan Murali, Antonio Pullini, Ciprian Seiculescu, Luca Benini
A floorplan-aware interactive tool flow for NoC design and synthesis. SoCC (2009)
Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan
De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs. DATE (2008)
Mohammad Reza Kakoee, Mohammad Riazati, Siamak Mohammadi
Enhancing the Testability of RTL Designs Using Efficiently Synthesized Assertions. ISQED (2008)
Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Siamak Mohammadi
Graph based test case generation for TLM functional verification. Microprocess. Microsystems 32 (5-6) (2008)
Mohammad Reza Kakoee, Mohammad Riazati, Siamak Mohammadi
Generating RTL Synthesizable Code from Behavioral Testbenches for Hardware-Accelerated Verification. DSD (2008)
Mohammad Reza Kakoee, Hamid Shojaei, Hassan Ghasemzadeh, Marjan Sirjani, Zainalabedin Navabi
A New Approach for Design and Verification of Transaction Level Models. ISCAS (2007)
Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi
On-Chip Verification of NoCs Using Assertion Processors. DSD (2007)
Mohammad Hossein Neishaburi, Mohammad Reza Kakoee, Masoud Daneshtalab, Saeed Safari
HW/SW architecture for soft-error cancellation in real-time operating system. IEICE Electron. Express 4 (23) (2007)
Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan
Reliable network-on-chip based on generalized de Bruijn graph. HLDVT (2007)
Mohammad Hossein Neishaburi, Masoud Daneshtalab, Mohammad Reza Kakoee, Saeed Safari
Improving Robustness of Real-Time Operating Systems (RTOS) Services Related to Soft-Errors. AICCSA (2007)
Mohammad Hossein Neishaburi, Mohammad Reza Kakoee, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi
A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services. DDECS (2007)
Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Masoud Daneshtalab, Saeed Safari
Assertion based design error diagnosis for core-based SoCs. SoCC (2007)
Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Siamak Mohammadi
Functional Test-Case Generation by a Control Transaction Graph for TLM Verification. DSD (2007)
Hassan Ghasemzadeh, Sepideh Mazrouee, Mohammad Reza Kakoee
Modified Pseudo LRU Replacement Algorithm. ECBS (2006)
Bijan Alizadeh, Mohammad Reza Kakoee
Using Integer Equations for High Level Formal Verification Property Checking. ISQED (2003)