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Mohammad Riazati
Publication Activity (10 Years)
Years Active: 2006-2023
Publications (10 Years): 9
Top Topics
Incentive Mechanism
Electronic Marketplaces
Neural Network
Top Venues
ICECS
Electron. Commer. Res.
ISQED
CoRR
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Publications
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Mahdi Taheri
,
Mohammad Riazati
,
Mohammad Hasan Ahmadilivani
,
Maksim Jenihhin
,
Masoud Daneshtalab
,
Jaan Raik
,
Mikael Sjödin
,
Björn Lisper
DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators.
CoRR
(2023)
Mahdi Taheri
,
Mohammad Riazati
,
Mohammad Hasan Ahmadilivani
,
Maksim Jenihhin
,
Masoud Daneshtalab
,
Jaan Raik
,
Mikael Sjödin
,
Björn Lisper
DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators.
ISQED
(2023)
Mohammad Loni
,
Hamid Mousavi
,
Mohammad Riazati
,
Masoud Daneshtalab
,
Mikael Sjödin
TAS: Ternarized Neural Architecture Search for Resource-Constrained Edge Devices.
DATE
(2022)
Mohammad Riazati
,
Masoud Daneshtalab
,
Mikael Sjödin
,
Björn Lisper
DeepFlexiHLS: Deep Neural Network Flexible High-Level Synthesis Directive Generator.
NorCAS
(2022)
Mohammad Riazati
,
Masoud Daneshtalab
,
Mikael Sjödin
,
Björn Lisper
AutoDeepHLS: Deep Neural Network High-level Synthesis using fixed-point precision.
AICAS
(2022)
Mohammad Riazati
,
Tara Ghasempouri
,
Masoud Daneshtalab
,
Jaan Raik
,
Mikael Sjödin
,
Björn Lisper
Adjustable self-healing methodology for accelerated functions in heterogeneous systems.
DSD
(2020)
Mohammad Riazati
,
Masoud Daneshtalab
,
Mikael Sjödin
,
Björn Lisper
DeepHLS: A complete toolchain for automatic synthesis of deep neural networks to FPGA.
ICECS
(2020)
Mohammad Riazati
,
Masoud Daneshtalab
,
Mikael Sjödin
,
Björn Lisper
SHiLA: Synthesizing High-Level Assertions for High-Speed Validation of High-Level Designs.
DDECS
(2020)
Mohammad Riazati
,
Mehdi Shajari
,
Siavash Khorsandi
An incentive mechanism to promote honesty among seller agents in electronic marketplaces.
Electron. Commer. Res.
19 (1) (2019)
Mohammad Reza Kakoee
,
Mohammad Riazati
,
Siamak Mohammadi
Enhancing the Testability of RTL Designs Using Efficiently Synthesized Assertions.
ISQED
(2008)
Mohammad Reza Kakoee
,
Mohammad Riazati
,
Siamak Mohammadi
Generating RTL Synthesizable Code from Behavioral Testbenches for Hardware-Accelerated Verification.
DSD
(2008)
Masoud Daneshtalab
,
A. Pedram
,
Mohammad Hossein Neishaburi
,
Mohammad Riazati
,
Ali Afzali-Kusha
,
Siamak Mohammadi
Distributing Congestions in NoCs through a Dynamic Routing Algorithm based on Input and Output Selections.
VLSI Design
(2007)
Mohammad Riazati
,
Ashkan Sobhani
,
M. Mottaghi-Dastjerdi
,
Ali Afzali-Kusha
,
Ali Khaki-Firooz
Low-power multiplier with static decision for input manipulation.
ISCAS
(2006)