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Generating RTL Synthesizable Code from Behavioral Testbenches for Hardware-Accelerated Verification.
Mohammad Reza Kakoee
Mohammad Riazati
Siamak Mohammadi
Published in:
DSD (2008)
Keyphrases
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hardware description language
integrated circuit
model checking
source code
low cost
human behavior
face verification
hardware design
programmable logic
information retrieval
artificial intelligence
formal analysis
field programmable gate array
formal verification
automatically generating
concurrent systems