Masoud Dehyadegari

Publication Activity (10 Years)

Years Active: 2005-2024
Publications (10 Years): 10

Top Topics

Error Minimization

Top Venues

Microelectron. J.

IEEE Trans. Computers

Comput. Electr. Eng.

Publications

Sina Shah Oveisi, Hoda Roodaki, Morteza Rezaalipour, Masoud Dehyadegari
A power-efficient approximate approach to improve the computational complexity of coding tools in versatile video coding. Multim. Tools Appl. 83 (28) (2024)
Alireza Dehghanpour, Javad Khodamoradi Kordestani, Masoud Dehyadegari
Accurate Low-Bit Length Floating-Point Arithmetic with Sorting Numbers. Neural Process. Lett. 55 (9) (2023)
Morteza Rezaalipour, Masoud Dehyadegari
Linear-time error calculation for approximate adders. Comput. Electr. Eng. 92 (2021)
Hoda Roodaki, Masoud Dehyadegari, Mahdi Nazm Bojnordi
G-Arrays: Geometric Arrays for Efficient Point Cloud Processing. ICASSP (2021)
Ananth Krishna Prasad, Morteza Rezaalipour, Masoud Dehyadegari, Mahdi Nazm Bojnordi
Memristive Data Ranking. HPCA (2021)
Morteza Rezaalipour, Mohammad Rezaalipour, Masoud Dehyadegari, Mahdi Nazm Bojnordi
AxMAP: Making Approximate Adders Aware of Input Patterns. IEEE Trans. Computers 69 (6) (2020)
Sarvenaz Tajasob, Morteza Rezaalipour, Masoud Dehyadegari
Designing energy-efficient imprecise adders with multi-bit approximation. Microelectron. J. 89 (2019)
Mohammad Amin Mosayebi, Arghavan Mohammad Hasani, Masoud Dehyadegari
Enhanced graph processing in PIM accelerators with improved queue management. Microelectron. J. 94 (2019)
Morteza Rezaalipour, Mohammad Rezaalipour, Sarvenaz Tajasob, Masoud Dehyadegari
IDrAx: A tool-chain for designing efficient approximate adders. Microelectron. J. 90 (2019)
Sarvenaz Tajasob, Morteza Rezaalipour, Masoud Dehyadegari, Mahdi Nazm Bojnordi
Designing Efficient Imprecise Adders using Multi-bit Approximate Building Blocks. ISLPED (2018)
Masoud Dehyadegari, Andrea Marongiu, Mohammad Reza Kakoee, Siamak Mohammadi, Nasser Yazdani, Luca Benini
Architecture Support for Tightly-Coupled Multi-Core Clusters with Shared-Memory HW Accelerators. IEEE Trans. Computers 64 (8) (2015)
Masoumeh Ebrahimi, Hannu Tenhunen, Masoud Dehyadegari
Fuzzy-based Adaptive Routing Algorithm for Networks-on-Chip. J. Syst. Archit. 59 (7) (2013)
Masoud Dehyadegari, Siamak Mohammadi, Nasser Yazdani
Distributed fair DRAM scheduling in network-on-chips architecture. J. Syst. Archit. 59 (7) (2013)
Masoud Dehyadegari, Andrea Marongiu, Mohammad Reza Kakoee, Luca Benini, Siamak Mohammadi, Nasser Yazdani
A tightly-coupled multi-core cluster with shared-memory HW accelerators. ICSAMOS (2012)
Masoud Dehyadegari, Masoud Daneshtalab, Masoumeh Ebrahimi, Juha Plosila, Siamak Mohammadi
An adaptive fuzzy logic-based routing algorithm for networks-on-chip. AHS (2011)
Mehdi Kamal, Neda Kazemian Amiri, Arezoo Kamran, Seyyed Alireza Hoseini, Masoud Dehyadegari, Hamid Noori
Dual-purpose custom instruction identification algorithm based on Particle Swarm Optimization. ASAP (2010)
Mohsen Nickray, Masoud Dehyadegari, Ali Afzali-Kusha
Power and delay optimization for network on chip. ECCTD (2005)