A multi-banked shared-l1 cache architecture for tightly coupled processor clusters.
Mohammad Reza KakoeeVladimir PetrovicLuca BeniniPublished in: ISSoC (2012)
Keyphrases
- tightly coupled
- loosely coupled
- shared memory multiprocessors
- memory hierarchy
- fine grained
- multithreading
- memory access
- memory subsystem
- general purpose
- memory management
- instruction set
- clustering algorithm
- parallel architecture
- high speed
- data access
- cache misses
- processor core
- multi processor
- embedded processors
- main memory
- shared memory
- multi core processors
- industry standard
- metadata
- multiprocessor systems
- ibm zenterprise