A DVFS Cycle Accurate Simulation Framework with Asynchronous NoC Design for Power-Performance Optimizations.
Davide ZoniFederico TerraneoWilliam FornaciariPublished in: J. Signal Process. Syst. (2016)
Keyphrases
- power reduction
- main contribution
- simulation environment
- power consumption
- design principles
- high accuracy
- conceptual framework
- high quality
- chip design
- computational framework
- simulation model
- design process
- design patterns
- mathematical model
- engineering design
- theoretical framework
- power dissipation
- simulation tool
- design space exploration
- user interface
- case study
- high level synthesis