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TPG: An untestability analyzer and test pattern generator for SEUs in the configuration memory of SRAM-based FPGAs.
Cinzia Bernardeschi
Luca Cassano
Andrea Domenici
Luca Sterpone
Published in:
Integr. (2016)
Keyphrases
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pattern generator
random access memory
memory usage
memory requirements
memory space
neural network
data structure
high dimensional
high speed
multi modal
power consumption
random access
optimal configuration