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ASSESS: A Simulator of Soft Errors in the Configuration Memory of SRAM-Based FPGAs.
Cinzia Bernardeschi
Luca Cassano
Andrea Domenici
Luca Sterpone
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2014)
Keyphrases
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random access memory
power consumption
memory requirements
test bed
memory usage
field programmable gate array
main memory
error analysis
memory space
error propagation
limited memory
real time
simulation model
data corruption