Heinrich Theodor Vierhaus

Publication Activity (10 Years)

Years Active: 1988-2020
Publications (10 Years): 16

Top Venues

DDECS

SPA

GI-Jahrestagung

IOLTS

Publications

Maksim Jenihhin, Said Hamdioui, Matteo Sonza Reorda, Milos Krstic, Peter Langendörfer, Christian Sauer, Anton Klotz, Michael Hübner, Jörg Nolte, Heinrich Theodor Vierhaus, Georgios N. Selimis, Dan Alexandrescu, Mottaqiallah Taouil, Geert Jan Schrijen, Jaan Raik, Luca Sterpone, Giovanni Squillero, Zoya Dyka
RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems. DATE (2020)
Maksim Jenihhin, Said Hamdioui, Matteo Sonza Reorda, Milos Krstic, Peter Langendörfer, Christian Sauer, Anton Klotz, Michael Hübner, Jörg Nolte, Heinrich Theodor Vierhaus, Georgios N. Selimis, Dan Alexandrescu, Mottaqiallah Taouil, Geert Jan Schrijen, Jaan Raik, Luca Sterpone, Giovanni Squillero, Zoya Dyka
RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems. CoRR (2019)
Farnoosh Hosseinzadeh, Petr Pfeifer, Heinrich Theodor Vierhaus
Optimal Dependability and Fine Granular Error Resilience Methodology for Reconfigurable Systems. DSD (2018)
Heinrich Theodor Vierhaus, Maksim Jenihhin, Matteo Sonza Reorda
RESCUE: Cross-Sectoral PhD Training Concept for Interdependent Reliability, Security and Quality. EWME (2018)
Heinrich Theodor Vierhaus
Migrating Electronic Systems from Fault Tolerant Computing to Error Resilience. SPA (2018)
Davide Dicorato, Petr Pfeifer, Heinrich Theodor Vierhaus
Fault detection and self repair in Hsiao-code FEC circuits. DDECS (2017)
Petr Pfeifer, Heinrich Theodor Vierhaus
Forward error correction in wireless communication systems for industrial applications. SPA (2017)
Petr Pfeifer, Farnoosh Hosseinzadeh, Heinrich Theodor Vierhaus
On comparison of robust configurable FPGA encoders for dependable industrial communication systems. IOLTS (2017)
Stefan Scharoba, Heinrich Theodor Vierhaus
Fast power overhead prediction for hardware redundancy-based fault tolerance. IOLTS (2017)
Farnoosh Hosseinzadeh, Petr Pfeifer, Heinrich Theodor Vierhaus
The coarse and fine granular fault tolerance techniques in FPGA-based processors. SPA (2017)
Christian Gleichner, Heinrich Theodor Vierhaus
Test and Diagnosis of Automotive Embedded Processors via High-Speed Standard Interfaces. J. Circuits Syst. Comput. 26 (8) (2017)
Stefan Scharoba, Heinrich Theodor Vierhaus
An Interactive Design Space Exploration Tool for Dependable Integrated Circuits. DSD (2016)
Christian Gleichner, Heinrich Theodor Vierhaus
Test of automotive embedded processors with high diagnostic resolution. DDECS (2016)
Petr Pfeifer, Heinrich Theodor Vierhaus
Iterative error correction with double/triple error detection. SPA (2016)
Mario Schölzel, Tobias Koal, Sebastian Müller, Stefan Scharoba, Stephanie Roder, Heinrich Theodor Vierhaus
A comprehensive software-based self-test and self-repair method for statically scheduled superscalar processors. LATS (2016)
Roberto Urban, Heinrich Theodor Vierhaus, Mario Schölzel, Enrico Altmann, Horst Seelig
Non-Cyclic Design Space Exploration for ASIPs - Compiler-Centered Microprocessor Design (CoMet). J. Circuits Syst. Comput. 25 (3) (2016)
Tobias Koal, Heinrich Theodor Vierhaus
Redundancy evaluation process of processor components for permanent fault compensation. AHS (2015)
Davide Dicorato, Heinrich Theodor Vierhaus
Detection and Correction of Logic Errors Using Extra Time Slots. GI-Jahrestagung (2015)
Christian Gleichner, Heinrich Theodor Vierhaus
Test eingebetteter Prozessoren im Zielsystem mit hoher diagnostischer Auflösung. GI-Jahrestagung (2015)
Tobias Koal, Stefan Scharoba, Heinrich Theodor Vierhaus
Combining Correction of Delay Faults and Transient Faults. DDECS (2015)
Roberto Urban, Mario Schölzel, Heinrich Theodor Vierhaus, Enrico Altmann, Horst Seelig
Compiler-Centred Microprocessor Design (CoMet) - From C-Code to a VHDL Model of an ASIP. DDECS (2015)
Ansgar Scherp, Steffen Becker, Heinrich Theodor Vierhaus
Doktorandenprogramm der INFORMATIK 2015. GI-Jahrestagung (2015)
Heinrich Theodor Vierhaus
Error resilience in nano-electronic digital circuits and systems. SPA (2015)
Raimund Ubar, Stephen Adeboye Oyeniran, Mario Schölzel, Heinrich Theodor Vierhaus
Multiple fault testing in systems-on-chip with high-level decision diagrams. IDT (2015)
Mario Schölzel, Heinrich Theodor Vierhaus
Fehlertolerante und energieeffiziente eingebettete Systeme: Methoden und Anwendungen. GI-Jahrestagung (2015)
Sebastian Müller, Tobias Koal, Stefan Scharoba, Heinrich Theodor Vierhaus, Mario Schölzel
A multi-layer software-based fault-tolerance approach for heterogenous multi-core systems. LATS (2015)
Tobias Koal, Mario Schölzel, Heinrich Theodor Vierhaus
Combining fault tolerance and self repair at minimum cost in power and hardware. DDECS (2014)
Sebastian Müller, Tobias Koal, Mario Schölzel, Heinrich Theodor Vierhaus
Timing for virtual TMR in logic circuits. IOLTS (2014)
Heinrich Theodor Vierhaus, Mario Schölzel, Jaan Raik, Raimund Ubar
Advanced technical education in the age of cyber physical systems. EWME (2014)
Roberto Urban, Kai Lehniger, Maximilian Heyne, Mario Schölzel, Heinrich Theodor Vierhaus
Vergleich der Beschreibung und Simulation einer Befehlssatzarchitektur in LISA und CoMet. MBMV (2014)
Mario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus
Diagnostic self-test for dynamically scheduled superscalar processors based on reconfiguration techniques for handling permanent faults. DFT (2014)
Mario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus
Systematic generation of diagnostic software-based self-test routines for processor components. ETS (2014)
Davide Sabena, Luca Sterpone, Mario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus, S. Wong, Robért Glein, Florian Rittner, C. Stender, Mario Porrmann, Jens Hagemeyer
Reconfigurable high performance architectures: How much are they ready for safety-critical applications? ETS (2014)
Sebastian Müller, Mario Schölzel, Heinrich Theodor Vierhaus
Towards a Graceful Degradable Multicore-System by Hierarchical Handling of Hard Errors. PDP (2013)
Petr Pfeifer, Zdenek Plíva, Mario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus
On performance estimation of a scalable VLIW soft-core in XILINX FPGAs. DDECS (2013)
Roberto Urban, Mario Schölzel, Heinrich Theodor Vierhaus
Ein konfigurierbarer Zwischencodesimulator zum compilerzentrierten Mikroprozessorentwurf. MBMV (2013)
Tobias Koal, Markus Ulbricht, Heinrich Theodor Vierhaus
Virtual TMR Schemes Combining Fault Tolerance and Self Repair. DSD (2013)
Mario Schölzel, Tobias Koal, Stephanie Roder, Heinrich Theodor Vierhaus
Towards an automatic generation of diagnostic in-field SBST for processor components. LATW (2013)
Tobias Koal, Markus Ulbricht, Piet Engelke, Heinrich Theodor Vierhaus
On the feasibility of combining on-line-test and self repair for logic circuits. DDECS (2013)
Christian Gleichner, Heinrich Theodor Vierhaus, Piet Engelke
Scan Based Tests via Standard Interfaces. DSD (2012)
Tobias Koal, Markus Ulbricht, Heinrich Theodor Vierhaus
Combining on-line fault detection and logic self repair. DDECS (2012)
Mario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus
An adaptive self-test routine for in-field diagnosis of permanent faults in simple RISC cores. DDECS (2012)
Markus Ulbricht, Heinrich Theodor Vierhaus, Tobias Koal
Activity Migration in M-of-N-Systems by Means of Load-Balancing. DSD (2012)
Sebastian Müller, Mario Schölzel, Heinrich Theodor Vierhaus
Hierarchical Self-repair in Heterogeneous Multi-core Systems by Means of a Software-based Reconfiguration. ARCS Workshops (2012)
Tobias Koal, Heinrich Theodor Vierhaus
Optimal spare utilization for reliability and mean lifetime improvement of logic built-in self-repair. DDECS (2011)
Tobias Koal, Daniel Scheit, Mario Schölzel, Heinrich Theodor Vierhaus
On the Feasibility of Built-In Self Repair for Logic Circuits. DFT (2011)
Markus Ulbricht, Mario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus
A new hierarchical built-in self-test with on-chip diagnosis for VLIW processors. DDECS (2011)
Tobias Koal, Heinrich Theodor Vierhaus
Combining de-stressing and self repair for long-term dependable systems. DDECS (2010)
Tobias Koal, Heinrich Theodor Vierhaus
A software-based self-test and hardware reconfiguration solution for VLIW processors. DDECS (2010)
René Kothe, Heinrich Theodor Vierhaus
Test Data and Power Reductions for Transition Delay Tests for Massive-Parallel Scan Structures. DSD (2010)
Tobias Koal, Daniel Scheit, Heinrich Theodor Vierhaus
A scheme of logic self repair including local interconnects. DDECS (2009)
Tobias Koal, Heinrich Theodor Vierhaus, Daniel Scheit
A Concept for Logic Self Repair. DSD (2009)
Tobias Koal, Daniel Scheit, Heinrich Theodor Vierhaus
Reliability Estimation Process. DSD (2009)
Silvio Misera, Heinrich Theodor Vierhaus, André Sieber
Simulated fault injections and their acceleration in SystemC. Microprocess. Microsystems 32 (5-6) (2008)
Tobias Koal, Heinrich Theodor Vierhaus
Basic Architecture for Logic Self Repair. IOLTS (2008)
Heinrich Theodor Vierhaus, René Kothe
Embedded Diagnostic Logic Test Exploiting Regularity. DSD (2008)
René Kothe, Heinrich Theodor Vierhaus
A Scan Controller Concept for Low Power Scan Tests. J. Low Power Electron. 4 (3) (2008)
Heinrich Theodor Vierhaus, Helmut Rossmann, Silvio Misera
Timing- / Power-Optimization for Digital Logic Based on Standard Cells. DSD (2007)
Silvio Misera, Heinrich Theodor Vierhaus, André Sieber
Fault Injection Techniques and their Accelerated Simulation in SystemC. DSD (2007)
R. Frost Brandenburg, D. Rudolph, Christian Galke, René Kothe, Heinrich Theodor Vierhaus
A Configurable Modular Test Processor and Scan Controller Architecture. IOLTS (2007)
René Kothe, Heinrich Theodor Vierhaus
Flip-Flops and Scan-Path Elements for Nanoelectronics. DDECS (2007)
René Kothe, Christian Galke, Sabine Schultke, Henry Fröschke, Steffen Gaede, Heinrich Theodor Vierhaus
Hardware/Software Based Hierarchical Self Test for SoCs. DDECS (2006)
Axel Vick, Helmut Rossmann, Heinrich Theodor Vierhaus
Timing-/Power-getriebener Layout-Entwurf für Zellen-basierte Digitalschaltungen. MBMV (2006)
Christian Galke, U. Gätzschmann, Heinrich Theodor Vierhaus
Scan-Based SoC Test Using Space / Time Pattern Compaction Schemes. DSD (2006)
Udo Krautz, Matthias Pflanz, Christian Jacobi, Hans-Werner Tast, Kai Weber, Heinrich Theodor Vierhaus
Evaluating coverage of error detection logic for soft errors using formal methods. DATE (2006)
Silvio Misera, Heinrich Theodor Vierhaus, Lars Breitenfeld, André Sieber
A Mixed Language Fault Simulation of VHDL and SystemC. DSD (2006)
S. Habermann, René Kothe, Heinrich Theodor Vierhaus
Built-in Self Repair by Reconfiguration of FPGAs. IOLTS (2006)
René Kothe, Heinrich Theodor Vierhaus, Torsten Coym, Wolfgang Vermeiren, Bernd Straube
Embedded Self Repair by Transistor and Gate Level Reconfiguration. DDECS (2006)
Christian Galke, René Kothe, Sabine Schultke, K. Winkler, Jeanette Honko, Heinrich Theodor Vierhaus
Embedded Scan Test with Diagnostic Features for Self-Testing SoCs. IOLTS (2006)
Christian Galke, René Kothe, Heinrich Theodor Vierhaus
Logic Self Repair. ARCS Workshops (2006)
Heinrich Theodor Vierhaus, Helmut Rossmann
Power-/Timing - Optimierung für Zellen-basierte Digitalschaltungen in Submikron-Technologien. GI Jahrestagung (1) (2005)
René Kothe, Christian Galke, Heinrich Theodor Vierhaus
A Multi-Purpose Concept for SoC Self Test Including Diagnostic Features. IOLTS (2005)
Marcin Gomulkiewicz, Miroslaw Kutylowski, Heinrich Theodor Vierhaus, Pawel Wlaz
Synchronization Fault Cryptanalysis for Breaking A5/1. WEA (2005)
Silvio Misera, Heinrich Theodor Vierhaus
FIT - A Parallel Hierarchical Fault Simulation Environment. PARELEC (2004)
Claudia Kretzschmar, Christian Galke, Heinrich Theodor Vierhaus
A Hierarchical Self Test Scheme for SoCs. IOLTS (2004)
Matthias Pflanz, K. Walther, Christian Galke, Heinrich Theodor Vierhaus
On-Line Techniques for Error Detection and Correction in Processor Registers with Cross-Parity Check. J. Electron. Test. 19 (5) (2003)
Matthias Pflanz, Heinrich Theodor Vierhaus
Control Signal Protection For High Performance Processors. IOLTS (2003)
Christian Galke, Marcus Grabow, Heinrich Theodor Vierhaus
Perspectives of Combining on-line and off-line Test Technology for Dependable Systems on a Chip. IOLTS (2003)
Christian Galke, Matthias Pflanz, Heinrich Theodor Vierhaus
A Test Processor Concept for Systems-on-a-Chip. ICCD (2002)
Christian Galke, Matthias Pflanz, Heinrich Theodor Vierhaus
On-line Detection and Compensation of Transient Errors in Processor Pipeline-Structures. IOLTW (2002)
Matthias Pflanz, K. Walther, Christian Galke, Heinrich Theodor Vierhaus
On-Line Error Detection and Correction in Storage Elements with Cross-Parity Check. IOLTW (2002)
Matthias Pflanz, K. Walther, Heinrich Theodor Vierhaus
On-line Error Detection Techniques for Dependable Embedded Processors with High Complexity. IOLTW (2001)
Matthias Pflanz, Heinrich Theodor Vierhaus
Online Check and Recovery Techniques for Dependable Embedded Processors. IEEE Micro 21 (5) (2001)
C. Rousselle, Matthias Pflanz, A. Behling, T. Mohaupt, Heinrich Theodor Vierhaus
A register-transfer-level fault simulator for permanent and transient faults in embedded processors. DATE (2001)
Matthias Pflanz, Christian Galke, Heinrich Theodor Vierhaus
A new method for on-line state machine observation for embedded microprocessors. HLDVT (2000)
Matthias Pflanz, Heinrich Theodor Vierhaus, F. Pompsch
An efficient on-line-test and back-up scheme for embedded processors. ITC (1999)
Fulvio Corno, Uwe Gläser, Paolo Prinetto, Matteo Sonza Reorda, Heinrich Theodor Vierhaus, Massimo Violante
SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (2) (1999)
Matthias Pflanz, Heinrich Theodor Vierhaus
Generating reliable embedded processors. IEEE Micro 18 (5) (1998)
H.-Ch. Dahmen, Uwe Gläser, Heinrich Theodor Vierhaus
An Efficient Dynamic Parallel Approach to Automatic Test Pattern Generation. Great Lakes Symposium on VLSI (1997)
Uwe Hübner, Heinrich Theodor Vierhaus, Raul Camposano
Partitioning and analysis of static digital CMOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (11) (1997)
H.-Ch. Dahmen, Uwe Gläser, Heinrich Theodor Vierhaus
A Parallel Approach Solving the Test Generation Problem for Synchronous Sequential Circuits. PARCO (1997)
H.-Ch. Dahmen, Uwe Gläser, Heinrich Theodor Vierhaus
Automatic Test Pattern Generation with Optimal Load Balancing. PVM (1996)
Jörg Wilberg, A. Kuth, Raul Camposano, Wolfgang Rosenstiel, Heinrich Theodor Vierhaus
A Design Exploration Environment. Great Lakes Symposium on VLSI (1996)
Uwe Gläser, Heinrich Theodor Vierhaus
Mixed level test generation for synchronous sequential circuits using the FOGBUSTER algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (4) (1996)
Uwe Gläser, Heinrich Theodor Vierhaus
FOGBUSTER: an efficient algorithm for sequential test generation. EURO-DAC (1995)
G. Van Brakel, Uwe Gläser, Hans G. Kerkhoff, Heinrich Theodor Vierhaus
Gate delay fault test generation for non-scan circuits. ED&TC (1995)
Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Uwe Gläser, Heinrich Theodor Vierhaus
Improving topological ATPG with symbolic techniques. VTS (1995)
Uwe Gläser, Heinrich Theodor Vierhaus, M. Kley, A. Wiederhold
Test generation for bridging faults in CMOS ICs based on current monitoring versus signal propagation. ICCAD (1994)
R. Wolber, Uwe Gläser, Heinrich Theodor Vierhaus
Testability Analysis for Test Generation in Synchronous Sequential Circuits. ICCD (1994)
Michel Langevin, Eduard Cerny, Jörg Wilberg, Heinrich Theodor Vierhaus
Local microcode generation in system design. Code Generation for Embedded Processors (1994)

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Publication Activity (10 Years)

Top Topics

Top Venues

Heinrich Theodor Vierhaus