Silvio Misera

Publication Activity (10 Years)

Years Active: 2004-2008
Publications (10 Years): 0

Publications

Silvio Misera, Heinrich Theodor Vierhaus, André Sieber
Simulated fault injections and their acceleration in SystemC. Microprocess. Microsystems 32 (5-6) (2008)
Heinrich Theodor Vierhaus, Helmut Rossmann, Silvio Misera
Timing- / Power-Optimization for Digital Logic Based on Standard Cells. DSD (2007)
Silvio Misera, Heinrich Theodor Vierhaus, André Sieber
Fault Injection Techniques and their Accelerated Simulation in SystemC. DSD (2007)
Silvio Misera, André Sieber
Hardwarenahe Fehlersimulation mit effektiven SystemC-Modellen. MBMV (2007)
Silvio Misera, Heinrich Theodor Vierhaus, Lars Breitenfeld, André Sieber
A Mixed Language Fault Simulation of VHDL and SystemC. DSD (2006)
Silvio Misera, Heinrich Theodor Vierhaus
FIT - A Parallel Hierarchical Fault Simulation Environment. PARELEC (2004)