Michel Langevin

Publication Activity (10 Years)

Years Active: 1990-2013
Publications (10 Years): 0

Top Topics

Optimization Methods

Memory Footprint

Top Venues

ACM Trans. Embed. Comput. Syst.

Publications

Claude Helmstetter, Sylvain Basset, Romain Lemaire, Fabien Clermidy, Pascal Vivet, Michel Langevin, Chuck Pilkington, Pierre G. Paulin, Didier Fuin
A dynamic stream link for efficient data flow control in NoC based heterogeneous MPSoC. ASP-DAC (2013)
Bruno Girodias, Luiza Gheorghe Iugan, Youcef Bouchebaba, Gabriela Nicolescu, El Mostapha Aboulhamid, Michel Langevin, Pierre G. Paulin
Integrating Memory Optimization with Mapping Algorithms for Multi-Processors System-on-Chip. ACM Trans. Embed. Comput. Syst. 11 (3) (2012)
Salim Ismail Al-Akhras, Sofiène Tahar, Gabriela Nicolescu, Michel Langevin, Pierre G. Paulin
On the Verification of a WiMax Design Using Symbolic Simulation. SCSS (2012)
Sébastien Le Beux, Guy Bois, Gabriela Nicolescu, Youcef Bouchebaba, Michel Langevin, Pierre G. Paulin
Combining mapping and partitioning exploration for NoC-based embedded systems. J. Syst. Archit. 56 (7) (2010)
Youcef Bouchebaba, Pierre G. Paulin, Ali Erdem Özcan, Bruno Lavigueur, Michel Langevin, Olivier Benny, Gabriela Nicolescu
MpAssign: A framework for solving the many-core platform mapping problem. International Symposium on Rapid System Prototyping (2010)
Bruno Girodias, Luiza Gheorghe, Youcef Bouchebaba, Gabriela Nicolescu, El Mostapha Aboulhamid, Michel Langevin, Pierre G. Paulin
Combining memory optimization with mapping of multimedia applications for multi-processors system-on-chip. International Symposium on Rapid System Prototyping (2010)
Sébastien Le Beux, Gabriela Nicolescu, Guy Bois, Youcef Bouchebaba, Michel Langevin, Pierre G. Paulin
Optimizing Configuration and Application Mapping for MPSoC Architectures. AHS (2009)
Karim Hadjiat, Francis St-Pierre, Guy Bois, Yvon Savaria, Michel Langevin, Pierre G. Paulin
An FPGA Implementation of a Scalable Network-on-Chip Based on the Token Ring Concept. ICECS (2007)
Pierre G. Paulin, Chuck Pilkington, Michel Langevin, Essaid Bensoudane, Olivier Benny, Damien Lyonnard, Bruno Lavigueur, David Lo
Distributed object models for multi-processor SoC's, with application to low-power multimedia wireless systems. DATE (2006)
Pierre G. Paulin, Chuck Pilkington, Michel Langevin, Essaid Bensoudane, Damien Lyonnard, Olivier Benny, Bruno Lavigueur, David Lo, Giovanni Beltrame, Vincent Gagné, Gabriela Nicolescu
Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia. IEEE Trans. Very Large Scale Integr. Syst. 14 (7) (2006)
Pierre G. Paulin, Chuck Pilkington, Michel Langevin, Essaid Bensoudane, Gabriela Nicolescu
Parallel programming models for a multi-processor SoC platform applied to high-speed traffic management. CODES+ISSS (2004)
Pierre G. Paulin, Chuck Pilkington, Essaid Bensoudane, Michel Langevin, Damien Lyonnard
Application of a Multi-Processor SoC Platform to High-Speed Packet Forwarding. DATE (2004)
Sofiène Tahar, Xiaoyu Song, Eduard Cerny, Zijian Zhou, Michel Langevin, Otmane Aït Mohamed
Modeling and formal verification of the Fairisle ATM switch fabricusing MDGs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (7) (1999)
Francisco Corella, Zijian Zhou, Xiaoyu Song, Michel Langevin, Eduard Cerny
Multiway Decision Graphs for Automated Hardware Verification. Formal Methods Syst. Des. 10 (1) (1997)
Eduard Cerny, Francisco Corella, Michel Langevin, Xiaoyu Song, Sofiène Tahar, Zijian Zhou
Verification with Abstract State Machines Using MDGs. Formal Hardware Verification (1997)
Michel Langevin, Eduard Cerny
A recursive technique for computing lower-bound performance of schedules. ACM Trans. Design Autom. Electr. Syst. 1 (4) (1996)
Zijian Zhou, Xiaoyu Song, Sofiène Tahar, Eduard Cerny, Francisco Corella, Michel Langevin
Formal Verification of the Island Tunnel Controller Using Multiway Decision Graphs. FMCAD (1996)
K. D. Anon, N. Boulerice, Eduard Cerny, Francisco Corella, Michel Langevin, Xiaoyu Song, Sofiène Tahar, Ying Xu, Zijian Zhou
MDG Tools for the Verification of RTL Designs. CAV (1996)
Michel Langevin, Sofiène Tahar, Zijian Zhou, Xiaoyu Song, Eduard Cerny
Behavioral Verification of an ATM Switch Fabric using Implicit Abstract State Enumeration. ICCD (1996)
Sofiène Tahar, Zijian Zhou, Xiaoyu Song, Eduard Cerny, Michel Langevin
Formal Verification of an ATM Switch Fabric using Multiway Decision Graphs. Great Lakes Symposium on VLSI (1996)
Zijian Zhou, Xiaoyu Song, Francisco Corella, Eduard Cerny, Michel Langevin
Partitioning transition relations efficiently and automatically. Great Lakes Symposium on VLSI (1995)
Francisco Corella, Michel Langevin, Eduard Cerny, Zijian Zhou, Xiaoyu Song
State enumeration with abstract descriptions of state machines. CHARME (1995)
Paul-Gerhard Plöger, Jörg Wilberg, Michel Langevin, Raul Camposano
WWW based structuring of codesigns. ISSS (1995)
Michel Langevin, Eduard Cerny
An Extended OBDD Representation for Extended FSMs. EDAC-ETC-EUROASIC (1994)
Michel Langevin, Eduard Cerny, Jörg Wilberg, Heinrich Theodor Vierhaus
Local microcode generation in system design. Code Generation for Embedded Processors (1994)
Michel Langevin, Eduard Cerny
A Recursive Technique for Computing Lower-Bound Performance of Schedules. ICCD (1993)
Michel Langevin, Eduard Cerny
Comparing Generic State Machines. CAV (1991)
Michel Langevin
Automated RTL Verification Based on Predicate Calculus. CAV (1990)
Michel Langevin
Automated RTL Verification Based on Predicate Calculus. CAV (DIMACS/AMS volume) (1990)