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Modeling and formal verification of the Fairisle ATM switch fabricusing MDGs.
Sofiène Tahar
Xiaoyu Song
Eduard Cerny
Zijian Zhou
Michel Langevin
Otmane Aït Mohamed
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1999)
Keyphrases
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formal verification
model checking
functional verification
symbolic model checking
automated verification
high speed
model checker
bounded model checking
orders of magnitude
first order logic
temporal logic
atm networks