Guy Bois

Publication Activity (10 Years)

Years Active: 1988-2024
Publications (10 Years): 7

Top Topics

Intrusion Detection

Invariant Recognition

Pose Estimation

Top Venues

IET Comput. Digit. Tech.

Publications

Julien Posso, Guy Bois, Yvon Savaria
Real-Time Spacecraft Pose Estimation Using Mixed-Precision Quantized Neural Network on COTS Reconfigurable MPSoC. CoRR (2024)
Julien Posso, Guy Bois, Yvon Savaria
Mobile-URSONet: an Embeddable Neural Network for Onboard Spacecraft Pose Estimation. CoRR (2022)
Julien Posso, Guy Bois, Yvon Savaria
Mobile-URSONet: an Embeddable Neural Network for Onboard Spacecraft Pose Estimation. ISCAS (2022)
Simon R. Girard, Vincent Legault, Guy Bois, Jean-François Boland
Avionics Graphics Hardware Performance Prediction with Machine Learning. Sci. Program. 2019 (2019)
Fellipe Montero, Guy Bois, Eric Jenn, Kevin Duplantier
. FPL (2016)
Shervin Vakili, J. M. Pierre Langlois, Guy Bois
Accuracy-aware processor customisation for fixed-point arithmetic. IET Comput. Digit. Tech. 10 (1) (2016)
Alexsandre B. Lacroix, J. M. Pierre Langlois, François-Raymond Boyer, Antoine Gosselin, Guy Bois
Node configuration for the Aho-Corasick algorithm in Intrusion Detection Systems. ANCS (2016)
Pascal Nsame, Guy Bois, Yvon Savaria
Analysis and characterization of data energy tradeoffs: For VLSI architectural agility in C-RAN platforms. ISCAS (2015)
Shervin Vakili, J. M. Pierre Langlois, Guy Bois
Designing customized microprocessors for fixed-point computation. AHS (2015)
Pascal Nsame, Guy Bois, Yvon Savaria
A data-driven energy efficient and flexible compute fabric architecture: For adaptive computing applied to ULSI of FFT. ICECS (2014)
Pascal Nsame, Guy Bois, Yvon Savaria
Adaptive real-time DSP acceleration for SoC applications. MWSCAS (2014)
Pascal Nsame, Guy Bois, Yvon Savaria
Design and Test of Adaptive Computing Fabrics for Scalable and High-Efficiency Cognitive SoC Applications. NATW (2014)
Shervin Vakili, J. M. Pierre Langlois, Guy Bois
Enhanced Precision Analysis for Accuracy-Aware Bit-Width Optimization Using Affine Arithmetic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (12) (2013)
Shervin Vakili, J. M. Pierre Langlois, Guy Bois
Finite-precision error modeling using affine arithmetic. ICASSP (2013)
Sébastien Le Beux, Ian O'Connor, Gabriela Nicolescu, Guy Bois, Pierre G. Paulin
Reduction methods for adapting optical network on chip topologies to 3D architectures. Microprocess. Microsystems 37 (1) (2013)
Shervin Vakili, J. M. Pierre Langlois, Guy Bois
Customised soft processor design: a compromise between architecture description languages and parameterisable processors. IET Comput. Digit. Tech. 7 (3) (2013)
Sébastien Le Beux, Jelena Trajkovic, Ian O'Connor, Gabriela Nicolescu, Guy Bois, Pierre G. Paulin
Optical Ring Network-on-Chip (ORNoC): Architecture and design methodology. DATE (2011)
Tennessee Carmel-Veilleux, Jean-François Boland, Guy Bois
A novel low-overhead flexible instrumentation framework for virtual platforms. International Symposium on Rapid System Prototyping (2011)
Shervin Vakili, Diana Carolina Gil, J. M. Pierre Langlois, Yvon Savaria, Guy Bois
Customized embedded processor design for global photographic tone mapping. ICECS (2011)
Sébastien Le Beux, Gabriela Nicolescu, Guy Bois, Pierre G. Paulin
A system-level exploration flow for optica network on chip (ONoC) in 3D MPSoC. ISCAS (2010)
Sébastien Le Beux, Jelena Trajkovic, Ian O'Connor, Gabriela Nicolescu, Guy Bois, Pierre G. Paulin
Multi-Optical Network-on-Chip for Large Scale MPSoC. IEEE Embed. Syst. Lett. 2 (3) (2010)
Sébastien Le Beux, Guy Bois, Gabriela Nicolescu, Youcef Bouchebaba, Michel Langevin, Pierre G. Paulin
Combining mapping and partitioning exploration for NoC-based embedded systems. J. Syst. Archit. 56 (7) (2010)
Michel Rogers-Vallée, Marc-André Cantin, Laurent Moss, Guy Bois
IP characterization methodology for fast and accurate power consumption estimation at transactional level model. ICCD (2010)
Sébastien Le Beux, Gabriela Nicolescu, Guy Bois, Youcef Bouchebaba, Michel Langevin, Pierre G. Paulin
Optimizing Configuration and Application Mapping for MPSoC Architectures. AHS (2009)
Nicolas Beucher, Normand Bélanger, Yvon Savaria, Guy Bois
High Acceleration for Video Processing Applications Using Specialized Instruction Set Based on Parallelism and Data Reuse. J. Signal Process. Syst. 56 (2-3) (2009)
Patrick Mahoney, Yvon Savaria, Guy Bois, Patrice Plante
Performance Characterization for the Implementation of Content Addressable Memories Based on Parallel Hashing Memories. Trans. High Perform. Embed. Archit. Compil. 2 (2009)
Mohamed H. Zaki, William Denman, Sofiène Tahar, Guy Bois
Integrating Abstraction Techniques for Formal Verification of Analog Designs. J. Aerosp. Comput. Inf. Commun. 6 (5) (2009)
Sebastien Fontaine, Sylvain Goyette, J. M. Pierre Langlois, Guy Bois
Acceleration of a 3D target tracking algorithm using an application specific instruction set processor. ICCD (2008)
Laurent Moss, Marc-André Cantin, Guy Bois, El Mostapha Aboulhamid
Automation of Communication Refinement and Hardware Synthesis within a System-Level Design Methodology. IEEE International Workshop on Rapid System Prototyping (2008)
Mohamed H. Zaki, Sofiène Tahar, Guy Bois
Formal verification of analog and mixed signal designs: A survey. Microelectron. J. 39 (12) (2008)
Sebastien Fontaine, Luc Filion, Guy Bois
Exploring ISS Abstractions for Embedded Software Design. DSD (2008)
Nicolas Beucher, Normand Bélanger, Yvon Savaria, Guy Bois
A Methodology to Evaluate the Energy Efficiency of Application Specific Processors. ICECS (2007)
Alena Tsikhanovich, El Mostapha Aboulhamid, Guy Bois
Communication Structure Refinement using Temporal Constraints Analysis. ICECS (2007)
Karim Hadjiat, Francis St-Pierre, Guy Bois, Yvon Savaria, Michel Langevin, Pierre G. Paulin
An FPGA Implementation of a Scalable Network-on-Chip Based on the Token Ring Concept. ICECS (2007)
Mohamed H. Zaki, Ghiath Al Sammane, Sofiène Tahar, Guy Bois
Combining Symbolic Simulation and Interval Arithmetic for the Verification of AMS Designs. FMCAD (2007)
Mohamed H. Zaki, Sofiène Tahar, Guy Bois
Qualitative Abstraction based Verification for Analog Circuits. ISoLA (2007)
Laurent Moss, Maxime de Nanclas, Luc Filion, Sebastien Fontaine, Guy Bois, El Mostapha Aboulhamid
Seamless hardware/software performance co-monitoring in a codesign simulation environment with RTOS support. DATE (2007)
Mohamed H. Zaki, Sofiène Tahar, Guy Bois
A practical approach for monitoring analog circuits. ACM Great Lakes Symposium on VLSI (2006)
Simon Provost, Bruno Lavigueur, Guy Bois, Gabriela Nicolescu
Integration of Configurable Processors in a Multiprocessor Platform. SoCC (2006)
Nicolas Beucher, Normand Bélanger, Yvon Savaria, Guy Bois
Motion Compensated Frame Rate Conversion Using a Specialized Instruction Set Processor. SiPS (2006)
Jérôme Chevalier, Maxime de Nanclas, Luc Filion, Olivier Benny, Mathieu Rondonneau, Guy Bois, El Mostapha Aboulhamid
A SystemC Refinement Methodology for Embedded Software. IEEE Des. Test Comput. 23 (2) (2006)
Alena Tsikhanovich, Frédéric Rousseau, El Mostapha Aboulhamid, Guy Bois
Transaction Level Modeling in Hardware/Software System Design using .Net Framework. CCECE (2006)
Alena Tsikhanovich, El Mostapha Aboulhamid, Guy Bois
A Methodology for Hw/Sw Specification and Simulation at Multiple Levels of Abstraction. IWSOC (2005)
Jean-Francois Thibeault, Mortimer Hubin, François Deslauriers, Patrick Samson, Guy Bois
A Reprogrammable SoC Design for a Real-Time Control Application. MSE (2005)
James Lapalme, El Mostapha Aboulhamid, Gabriela Nicolescu, Luc Charest, François R. Boyer, J. P. David, Guy Bois
ESys.Net: a new solution for embedded systems modeling and simulation. LCTES (2004)
D. Quinn, Bruno Lavigueur, Guy Bois, El Mostapha Aboulhamid
A System Level Exploration Platform and Methodology for Network Applications Based on Configurable Processors. DATE (2004)
Luc Charest, El Mostapha Aboulhamid, Guy Bois
Using Design Patterns for Type Unification and Introspection in SystemC. IWSOC (2004)
James Lapalme, El Mostapha Aboulhamid, Gabriela Nicolescu, Luc Charest, François R. Boyer, J. P. David, Guy Bois
.NET Framework - A Solution for the Next Generation Tools for System-Level Modeling and Simulation. DATE (2004)
S. Regimbal, Yvon Savaria, Guy Bois
Verification Strategy Determination Using Dependence Analysis of Transaction-Level Models. IWSOC (2004)
Marc Bertola, Guy Bois
A methodology for the design of AHB bus master wrappers. DSD (2003)
S. Regimbal, Jean-Francois Lemire, Yvon Savaria, Guy Bois, El Mostapha Aboulhamid, A. Baron
Automating Functional Coverage Analysis Based on an Executable Specification. IWSOC (2003)
Marc Bertola, Guy Bois
Teaching Bus Architectures with a Basic, Hands-On SOC Platform. MSE (2003)
Jérôme Chevalier, Mathieu Rondonneau, Olivier Benny, Guy Bois, El Mostapha Aboulhamid, François R. Boyer
SPACE: A Hardware/Software SystemC Modeling Platform Including an RTOS. FDL (2003)
Luc Charest, Michel Reid, El Mostapha Aboulhamid, Guy Bois
A methodology for interfacing open source systemC with a third party software. DATE (2001)
Mohamed Nekili, Yvon Savaria, Guy Bois
Minimizing process-induced skew using delay tuning. ISCAS (4) (2001)
Mohamed Nekili, Yvon Savaria, Guy Bois
Spatial characterization of process variations via MOS transistor time constants in VLSI and WSI. IEEE J. Solid State Circuits 34 (1) (1999)
B. Bosi, Guy Bois, Yvon Savaria
Reconfigurable pipelined 2-D convolvers for fast digital signal processing. IEEE Trans. Very Large Scale Integr. Syst. 7 (3) (1999)
B. Le Chapelain, A. Mechain, Yvon Savaria, Guy Bois
Development of a high performance TSPC library for implementation of large digital building blocks. ISCAS (1) (1999)
Mohamed Nekili, Yvon Savaria, Guy Bois
Design of Clock Distribution Networks in Presence of Process Variations. Great Lakes Symposium on VLSI (1998)
Manoucher Shaditalab, Guy Bois, Mohamad Sawan
Self Sorting Radix_2 FFT on FPGA using Parallel Pipelined Distributed Arithmetic Blocks. FCCM (1998)
Mohamed Nekili, Guy Bois, Yvon Savaria
Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations. IEEE Trans. Very Large Scale Integr. Syst. 5 (2) (1997)
Guy Bois, Eduard Cerny
Efficient generation of diagonal constraints for 2-D mask compaction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (9) (1996)
Mohamed Nekili, Yvon Savaria, Guy Bois
A Fast Low-Power Driver for Long Interconnections in VLSI Systems. ISCAS (1994)
Eduard Cerny, El Mostapha Aboulhamid, Guy Bois, Jocelyn Cloutier
Built-in self-test of a CMOS ALU. IEEE Des. Test 5 (4) (1988)