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Integrating Abstraction Techniques for Formal Verification of Analog Designs.

Mohamed H. ZakiWilliam DenmanSofiène TaharGuy Bois
Published in: J. Aerosp. Comput. Inf. Commun. (2009)
Keyphrases
  • formal verification
  • bounded model checking
  • model checking
  • model checker
  • automated verification
  • symbolic model checking
  • signal processing
  • program slicing
  • temporal logic
  • high level
  • circuit design