Mohamed Nekili

Publication Activity (10 Years)

Years Active: 1993-2012
Publications (10 Years): 0

Top Venues

Int. J. Circuit Theory Appl.

Publications

Falah R. Awwad, Mohamed Nekili, Mohamad Sawan
A novel theory on parallel repeater-insertion methodologies for long on-chip interconnects. Int. J. Circuit Theory Appl. 40 (7) (2012)
Falah R. Awwad, Mohamed Nekili, Venkatanarayana Ramachandran, Mohamad Sawan
On Modeling of Parallel Repeater-Insertion Methodologies for SoC Interconnects. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2008)
A. Landry, Mohamed Nekili, Yvon Savaria
A novel 2 GHz multi-layer AMBA high-speed bus interconnect matrix for SoC platforms. ISCAS (4) (2005)
Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili
Simultaneous adaptive wire adjustment and local topology modification for tuning a bounded-skew clock tree. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (10) (2005)
Adhir Upadhyay, Syed Rafay Hasan, Mohamed Nekili
Optimal partitioning of globally asychronous locally synchronous processor arrays. ACM Great Lakes Symposium on VLSI (2004)
Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili
Adaptive wire adjustment for bounded skew Clock Distribution Network. ASP-DAC (2003)
Falah R. Awwad, Mohamed Nekili
Variable-segment & variable-driver parallel regeneration techniques for RLC VLSI interconnects. ACM Great Lakes Symposium on VLSI (2002)
Bill Pontikakis, Mohamed Nekili
A novel double edge-triggered pulse-clocked TSPC D flip-flop for high-performance and low-power VLSI design applications. ISCAS (5) (2002)
Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili
Quadratic deferred-merge embedding algorithm for zero skew clock distribution network. Timing Issues in the Specification and Synthesis of Digital Systems (2002)
Mohamed Nekili, Yvon Savaria, Guy Bois
Minimizing process-induced skew using delay tuning. ISCAS (4) (2001)
Mohamed Nekili, Yvon Savaria, Guy Bois
Spatial characterization of process variations via MOS transistor time constants in VLSI and WSI. IEEE J. Solid State Circuits 34 (1) (1999)
Mohamed Nekili, Yvon Savaria, Guy Bois
Design of Clock Distribution Networks in Presence of Process Variations. Great Lakes Symposium on VLSI (1998)
Mohamed Nekili, Guy Bois, Yvon Savaria
Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations. IEEE Trans. Very Large Scale Integr. Syst. 5 (2) (1997)
Mohamed Nekili, Yvon Savaria, Guy Bois
A Fast Low-Power Driver for Long Interconnections in VLSI Systems. ISCAS (1994)
Mohamed Nekili, Yvon Savaria
Parallel Regeneration of Interconnections in VLSI & ULSI Circuits. ISCAS (1993)