A novel double edge-triggered pulse-clocked TSPC D flip-flop for high-performance and low-power VLSI design applications.
Bill PontikakisMohamed NekiliPublished in: ISCAS (5) (2002)
Keyphrases
- low power
- vlsi design
- power dissipation
- low power consumption
- signal processor
- power consumption
- cmos technology
- flip flops
- low cost
- high speed
- design methodology
- single chip
- edge detection
- digital signal processing
- logic circuits
- vlsi circuits
- multiple input
- power reduction
- mixed signal
- image sensor
- signal processing
- gate array
- neural network
- ultra low power
- low voltage
- image processing