Normand Bélanger

Publication Activity (10 Years)

Years Active: 1994-2019
Publications (10 Years): 10

Top Topics

Signal Processing

Classification Algorithm

Enabling Technologies

Top Venues

Publications

Thibaut Stimpfling, Normand Bélanger, J. M. Pierre Langlois, Yvon Savaria
SHIP: A Scalable High-Performance IPv6 Lookup Algorithm That Exploits Prefix Characteristics. IEEE/ACM Trans. Netw. 27 (4) (2019)
Bachir Fradj, Benjamin Wolff, Normand Bélanger, Yvon Savaria
Implementation of a Cache-Based IPv6 Lookup System with Hashing. ISCAS (2018)
Thibaut Stimpfling, J. M. Pierre Langlois, Normand Bélanger, Yvon Savaria
A Low-Latency Memory-Efficient IPv6 Lookup Engine Implemented on FPGA Using High-Level Synthesis. CCGrid (2018)
Benjamin Wolff, Bachir Fradj, Normand Bélanger, Yvon Savaria
Extending a CPU Cache for Efficient IPv6 Lookup. MWSCAS (2018)
Thibaut Stimpfling, Normand Bélanger, J. M. Pierre Langlois, Yvon Savaria
SHIP: A Scalable High-performance IPv6 Lookup Algorithm that Exploits Prefix Characteristics. CoRR (2017)
Thibaut Stimpfling, Normand Bélanger, Omar Cherkaoui, André Béliveau, Ludovic Béliveau, Yvon Savaria
Extensions to decision-tree based packet classification algorithms to address new classification paradigms. Comput. Networks 122 (2017)
Imad Benacer, François-Raymond Boyer, Normand Bélanger, Yvon Savaria
A fast systolic priority queue architecture for a flow-based Traffic Manager. NEWCAS (2016)
Roya Alizadeh, Normand Bélanger, Yvon Savaria, François R. Boyer
Performance characterization of an SCMA decoder. NEWCAS (2016)
Roya Alizadeh, Normand Bélanger, Yvon Savaria, Jean-François Frigon
DPDK and MKL; Enabling technologies for near deterministic cloud-based signal processing. NEWCAS (2015)
Hanieh Abdollahifakhr, Normand Bélanger, Yvon Savaria, François Gagnon
Power-efficient hardware architecture for computing Split-Radix FFTs on highly sparsed spectrum. NEWCAS (2015)
Gilbert Kowarzyk, Normand Bélanger, David Haccoun, Yvon Savaria
Optimizing the Parallel Tree-Search for Finding Shortest-Span Error-Correcting CDO Codes. IEEE Trans. Parallel Distributed Syst. 25 (11) (2014)
Thibaut Stimpfling, Yvon Savaria, André Béliveau, Normand Bélanger, Omar Cherkaoui
Optimal packet classification applicable tothe OpenFlow context. HPPN@HPDC (2013)
Gilbert Kowarzyk, Normand Bélanger, David Haccoun, Yvon Savaria
Efficient Parallel Search Algorithm for Determining Optimal R=1/2 Systematic Convolutional Self-Doubly Orthogonal Codes. IEEE Trans. Commun. 61 (3) (2013)
Mame Maria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre
Loop Acceleration Exploration for ASIP Architecture. IEEE Trans. Very Large Scale Integr. Syst. 20 (4) (2012)
Syed Rafay Hasan, Normand Bélanger, Yvon Savaria, M. Omair Ahmad
All digital skew tolerant synchronous interfacing methods for high-performance point-to-point communications in deep sub-micron SoCs. Integr. 44 (1) (2011)
Gilbert Kowarzyk, Normand Bélanger, Yvon Savaria
A GPGPU-based software implementation of the PBDI deinterlacing algorithm. ICECS (2011)
Syed Rafay Hasan, Normand Bélanger, Yvon Savaria, M. Omair Ahmad
Crosstalk-Glitch Gating: A Solution for Designing Glitch-Tolerant Asynchronous Handshake Interface Mechanisms for GALS Systems. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2010)
Syed Rafay Hasan, Normand Bélanger, Yvon Savaria, M. Omair Ahmad
Crosstalk Glitch Propagation Modeling for Asynchronous Interfaces in Globally Asynchronous Locally Synchronous Systems. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2010)
Nicolas Beucher, Normand Bélanger, Yvon Savaria, Guy Bois
High Acceleration for Video Processing Applications Using Specialized Instruction Set Based on Parallelism and Data Reuse. J. Signal Process. Syst. 56 (2-3) (2009)
Maria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre
Loop-oriented metrics for exploring an application-specific architecture design-space. ASAP (2008)
Nicolas Beucher, Normand Bélanger, Yvon Savaria, Guy Bois
A Methodology to Evaluate the Energy Efficiency of Application Specific Processors. ICECS (2007)
Mame Maria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre
A Novel Application-specific Instruction-set Processor Design Approach for Video Processing Acceleration. J. VLSI Signal Process. 47 (3) (2007)
Maria Mbaye, D. Lebel, Normand Bélanger, Yvon Savaria, Samuel Pierre
Design exploration with an application-specific instruction-set processor for ELA deinterlacing. ISCAS (2006)
Nicolas Beucher, Normand Bélanger, Yvon Savaria, Guy Bois
Motion Compensated Frame Rate Conversion Using a Specialized Instruction Set Processor. SiPS (2006)
Maria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre
Application specific instruction-set processor generation for video processing based on loop optimization. ISCAS (4) (2005)
Normand Bélanger, David Haccoun, Yvon Savaria
A multiprocessor architecture for multiple path stack sequential decoders. IEEE Trans. Commun. 42 (234) (1994)