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A Low-Latency Memory-Efficient IPv6 Lookup Engine Implemented on FPGA Using High-Level Synthesis.
Thibaut Stimpfling
J. M. Pierre Langlois
Normand Bélanger
Yvon Savaria
Published in:
CCGrid (2018)
Keyphrases
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memory efficient
low latency
high level synthesis
high speed
parallel architecture
real time
high throughput
ip address
highly efficient
signal processing
hardware implementation
virtual machine
stream processing
multi dimensional
data acquisition
monitoring system
low cost
database systems