Timing for virtual TMR in logic circuits.

Sebastian Müller Tobias Koal Mario Schölzel Heinrich Theodor Vierhaus

Published in: IOLTS (2014)

Keyphrases

logic circuits
low power
functional decomposition
tunnel diode
virtual reality
virtual environment
augmented reality
gate array
pattern recognition
virtual world
low cost
neural network
membership functions
power consumption
logic synthesis