Gate delay fault test generation for non-scan circuits.
G. Van BrakelUwe GläserHans G. KerkhoffHeinrich Theodor VierhausPublished in: ED&TC (1995)
Keyphrases
- test generation
- cmos technology
- power dissipation
- test cases
- fault models
- fault diagnosis
- test sequences
- design automation
- power consumption
- symbolic execution
- quality assurance
- multiple input
- fault detection
- low power
- mutation testing
- static analysis
- software testing
- high speed
- circuit design
- digital signal processing
- test data generation
- fault management
- data sets
- pattern matching
- query language
- case study
- image processing
- fault model
- real world
- field effect transistors
- neural network