Luis Entrena

Publication Activity (10 Years)

Years Active: 1993-2024
Publications (10 Years): 17

Top Topics

Hardware Designs

Ionizing Radiation

Random Number Generators

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Luis Ángel García-Astudillo, Almudena Lindoso, Luis Entrena
Error Mitigation Using Optimized Redundancy for Composite Algorithms in FPGAs. IEEE Trans. Aerosp. Electron. Syst. 60 (2) (2024)
German Leon, José M. Badía, Jose A. Belloch, Almudena Lindoso, Luis Entrena
Comparative analysis of soft-error sensitivity in LU decomposition algorithms on diverse GPUs. J. Supercomput. 80 (9) (2024)
Honorio Martín, Sophie Dupuis, Giorgio Di Natale, Luis Entrena
Using Approximate Circuits Against Hardware Trojans. IEEE Des. Test 40 (3) (2023)
Luis Entrena, Antonio J. Sanchez-Clemente, Luis Ángel García-Astudillo, Marta Portela-García, Mario García-Valderas, Almudena Lindoso, Roberto Sarmiento
Formal Verification of Fault-Tolerant Hardware Designs. IEEE Access 11 (2023)
Pablo M. Aviles, Jose A. Belloch, Luis Entrena, Almudena Lindoso
Supervised Triple Macrosynchronized Lockstep (STMLS) Architecture for Multicore Processors. IEEE Access 11 (2023)
Luis Ángel García-Astudillo, Luis Entrena, Almudena Lindoso, Honorio Martín
Reduced Resolution Redundancy: A Novel Approximate Error Mitigation Technique. IEEE Access 10 (2022)
Lucas Matana Luza, Frederic Wrobel, Luis Entrena, Luigi Dilillo
Impact of Atmospheric and Space Radiation on Sensitive Electronic Devices. ETS (2022)
Luis Ángel García-Astudillo, Almudena Lindoso, Marta Portela, Luis Entrena
Evaluation of a Reduced Precision Redundancy FFT Design. DCIS (2020)
Carmen Camara, Honorio Martín, Pedro Peris-Lopez, Luis Entrena
A True Random Number Generator Based on Gait Data for the Internet of You. IEEE Access 8 (2020)
Honorio Martín, Luis Entrena, Sophie Dupuis, Giorgio Di Natale
A Novel Use of Approximate Circuits to Thwart Hardware Trojan Insertion and Provide Obfuscation. IOLTS (2018)
Antonio Sanchez-Clemente, Luis Entrena, Fernanda Lima Kastensmidt
Approximate TMR for selective error mitigation in FPGAs based on testability analysis. AHS (2018)
Honorio Martín, Giorgio Di Natale, Luis Entrena
Towards a Dependable True Random Number Generator With Self-Repair Capabilities. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2018)
Manuel Peña-Fernandez, Almudena Lindoso, Luis Entrena, Mario García-Valderas, S. Philippe, Yolanda Morilla, Pedro Martin-Holgado
PTM-based hybrid error-detection architecture for ARM microprocessors. Microelectron. Reliab. (2018)
Honorio Martín, Pedro Martin-Holgado, Pedro Peris-Lopez, Yolanda Morilla, Luis Entrena
On the Entropy of Oscillator-Based True Random Number Generators under Ionizing Radiation. Entropy 20 (7) (2018)
Boyang Du, Matteo Sonza Reorda, Luca Sterpone, Luis Parra, Marta Portela-García, Almudena Lindoso, Luis Entrena
Online Test of Control Flow Errors: A New Debug Interface-Based Approach. IEEE Trans. Computers 65 (6) (2016)
Antonio Sanchez-Clemente, Luis Entrena, Radek Hrbacek, Lukás Sekanina
Error Mitigation Using Approximate Logic Circuits: A Comparison of Probabilistic and Evolutionary Approaches. IEEE Trans. Reliab. 65 (4) (2016)
Antonio Martínez-Álvarez, Felipe Restrepo-Calle, Sergio Cuenca-Asensi, Leonardo M. Reyneri, Almudena Lindoso, Luis Entrena
A Hardware-Software Approach for On-Line Soft Error Mitigation in Interrupt-Driven Applications. IEEE Trans. Dependable Secur. Comput. 13 (4) (2016)
Boyang Du, Matteo Sonza Reorda, Luca Sterpone, Luis Parra, Marta Portela-García, Almudena Lindoso, Luis Entrena
A new solution to on-line detection of Control Flow Errors. IOLTS (2014)
Antonio Sanchez-Clemente, Luis Entrena, Mario García-Valderas
Error masking with approximate logic circuits using dynamic probability estimations. IOLTS (2014)
M. Arévalo-Garbayo, Marta Portela-García, Mario García-Valderas, Celia López-Ongil, Luis Entrena
A method to assess the robustness of cryptographic circuits at the design stage. Microelectron. J. 45 (10) (2014)
Luis Entrena
Fast fault injection techniques using FPGAs. LATW (2013)
Boyang Du, Matteo Sonza Reorda, Luca Sterpone, Luis Parra, Marta Portela-García, Almudena Lindoso, Luis Entrena
Exploiting the debug interface to support on-line test of control flow errors. IOLTS (2013)
Marta Portela-García, Michelangelo Grosso, M. Gallardo-Campos, Matteo Sonza Reorda, Luis Entrena, Mario García-Valderas, Celia López-Ongil
On the use of embedded debug features for permanent and transient fault resilience in microprocessors. Microprocess. Microsystems 36 (5) (2012)
Antonio Sanchez-Clemente, Luis Entrena, Mario García-Valderas, Celia López-Ongil
Logic masking for SET Mitigation Using Approximate Logic Circuits. IOLTS (2012)
Marta Portela-García, Almudena Lindoso, Luis Entrena, Mario García-Valderas, Celia López-Ongil, N. Marroni, Bernardo Pianta, Letícia Maria Bolzani Poehls, Fabian Vargas
Evaluating the Effectiveness of a Software-Based Technique Under SEEs Using FPGA-Based Fault Injection Approach. J. Electron. Test. 28 (6) (2012)
Celia López-Ongil, Marta Portela-García, Mario García-Valderas, Anna Vaskova, Luis Entrena, Joaquín Rivas-Abalo, Alberto Martín-Ortega, Javier Martinez-Oter, S. Rodriguez-Bustabad, Ignacio Arruego
SEU sensitivity of robust communication protocols. IOLTS (2012)
Luis Entrena, Mario García-Valderas, Raúl Fernández Cardenal, Almudena Lindoso, Marta Portela-García, Celia López-Ongil
Soft Error Sensitivity Evaluation of Microprocessors by Multilevel Emulation-Based Fault Injection. IEEE Trans. Computers 61 (3) (2012)
Anna Vaskova, Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena
Evaluation techniques for on-line testing of robust systems based on critical tasks distribution. IOLTS (2011)
Marta Portela-García, Almudena Lindoso, Luis Entrena, Mario García-Valderas, Celia López-Ongil, Bernardo Pianta, Letícia Maria Bolzani Poehls, Fabian Vargas
Using an FPGA-based fault injection technique to evaluate software robustness under SEEs: A case study. LATW (2011)
Anna Vaskova, Celia López-Ongil, Enrique San Millán, Alejandro Jiménez-Horas, Luis Entrena
Accelerating secure circuit design with hardware implementation of Diehard Battery of tests of randomness. IOLTS (2011)
Marta Portela-García, Celia López-Ongil, Mario García-Valderas, Luis Entrena
Fault Injection in Modern Microprocessors Using On-Chip Debugging Infrastructures. IEEE Trans. Dependable Secur. Comput. 8 (2) (2011)
Honorio Martín, Enrique San Millán, Luis Entrena, Julio César Hernández Castro, Pedro Peris-Lopez
AKARI-X: A pseudorandom number generator for secure lightweight systems. IOLTS (2011)
Anna Vaskova, Celia López-Ongil, Alejandro Jiménez-Horas, Enrique San Millán, Luis Entrena
Robust cryptographic ciphers with on-line statistical properties validation. IOLTS (2010)
Michelangelo Grosso, Matteo Sonza Reorda, Marta Portela-García, Mario García-Valderas, Celia López-Ongil, Luis Entrena
An on-line fault detection technique based on embedded debug features. IOLTS (2010)
Pedro Peris-Lopez, Enrique San Millán, Jan C. A. van der Lubbe, Luis Entrena
Cryptographically secure pseudo-random bit generator for RFID tags. ICITST (2010)
Mario García-Valderas, Marta Portela-García, Celia López-Ongil, Luis Entrena
In-depth analysis of digital circuits against soft errors for selective hardening. IOLTS (2009)
Marta Portela-García, Mario García-Valderas, Celia López-Ongil, Luis Entrena, B. Lestriez, Luis Berrojo
Study of SEU effects in a Turbo Decoder Bit Error Rate. LATW (2009)
Alejandro Jiménez-Horas, Enrique San Millán, Celia López-Ongil, Marta Portela-García, Mario García-Valderas, Luis Entrena
Pseudo-random number generation applied to robust modern cryptography: A new technique for block ciphers. IOLTS (2009)
Mario García-Valderas, Luis Entrena, Raúl Fernández Cardenal, Celia López-Ongil, Marta Portela-García
SET Emulation Under a Quantized Delay Model. J. Electron. Test. 25 (1) (2009)
Fabian Vargas, Claudia A. Rocha, Bernardo Pianta, Marta Portela-García, Celia López-Ongil, Mario García-Valderas, Luis Entrena
Briefing power/reliability optimization in embedded software design. IOLTS (2009)
Celia López-Ongil, Alejandro Jiménez-Horas, Marta Portela-García, Mario García-Valderas, Enrique San Millán, Luis Entrena
Smart Hardening for Round-based Encryption Algorithms: Application to Advanced Encryption Standard. IOLTS (2008)
Almudena Lindoso, Luis Entrena, Juan Izquierdo, Judith Liu-Jimenez
Coarse-grain dynamically reconfigurable coprocessor for image processing in SOPC. FPL (2008)
Enrique San Millán, Luis Entrena, José Alberto Espejo
Logic Transformations by Multiple Wire Network Addition. DSD (2008)
Almudena Lindoso, Luis Entrena, Judith Liu-Jimenez
Wavelet-Based Fingerprint Region Selection. CAIP (2007)
Mario García-Valderas, Raúl Fernández Cardenal, Celia López-Ongil, Marta Portela-García, Luis Entrena
SET Emulation Under a Quantized Delay Model. DFT (2007)
Almudena Lindoso, Luis Entrena, Judith Liu-Jimenez, Enrique San Millán
Correlation-Based Fingerprint Matching with Orientation Field Alignment. ICB (2007)
Michael G. Lorenz, Luis Mengibar, Enrique San Millán, Luis Entrena
Low power data processing system with self-reconfigurable architecture. J. Syst. Archit. 53 (9) (2007)
Marta Portela-García, Celia López-Ongil, Mario García-Valderas, Luis Entrena
A Rapid Fault Injection Approach for Measuring SEU Sensitivity in Complex Processors. IOLTS (2007)
Almudena Lindoso, Luis Entrena
High performance FPGA-based image correlation. J. Real Time Image Process. 2 (4) (2007)
Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Marta Portela-García, Celia López-Ongil, Luis Entrena
Fault Injection-based Reliability Evaluation of SoPCs. ETS (2006)
Mario García-Valderas, Marta Portela-García, Celia López-Ongil, Luis Entrena
Emulation-based Fault Injection in Circuits with Embedded Memories. IOLTS (2006)
Almudena Lindoso, Luis Entrena, Celia López-Ongil, Judith Liu-Jimenez
Correlation-Based Fingerprint Matching Using FPGAs. FPT (2005)
Michael G. Lorenz, Luis Mengibar, Mario García-Valderas, Luis Entrena
Power Consumption Reduction Through Dynamic Reconfiguration. FPL (2004)
Celia López-Ongil, Raul Sánchez-Reillo, Judith Liu-Jimenez, Fernando Casado, Leslie Sánchez, Luis Entrena
FPGA Implementation of Biometric Authentication System Based on Hand Geometry. FPL (2004)
Raul Sánchez-Reillo, Judith Liu-Jimenez, Luis Entrena
Architectures for Biometric Match-on-Token Solutions. ECCV Workshop BioAW (2004)
Mario García-Valderas, Celia López-Ongil, Marta Portela-García, Luis Entrena
Transient Fault Emulation of Hardened Circuits in FPGA Platforms. IOLTS (2004)
Luis Mengibar, Luis Entrena, Michael G. Lorenz, Raul Sánchez-Reillo
State Encoding for Low-Power FSMs in FPGA. PATMOS (2003)
Michael G. Lorenz, Luis Mengibar, Luis Entrena, Raul Sánchez-Reillo
Data Processing System With Self-reconfigurable Architecture, for Low Cost, Low Power Applications. FPL (2003)
Enrique San Millán, Luis Entrena, José Alberto Espejo, Celia López
Theoretical comparison between sequential redundancy addition and removal and retiming optimization techniques. J. Syst. Archit. 49 (12-15) (2003)
Luis Berrojo, Isabel González, Luis Entrena, Celia López, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
Analysis of the Equivalences and Dominances of Transient Faults at the RT Level. IOLTW (2002)
Luis Berrojo, Isabel González, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Luis Entrena, Celia López
New Techniques for Speeding-Up Fault-Injection Campaigns. DATE (2002)
Luis Berrojo, Isabel González, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Luis Entrena, Celia López
An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation. VTS (2002)
José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías
Generalized reasoning scheme for redundancy addition and removal logic optimization. DATE (2001)
Enrique San Millán, Luis Entrena, José Alberto Espejo
On the Optimization Power of Redundancy Addition and Removal Techniques for Sequential Circuits. ICCAD (2001)
Luis Entrena, Celia López, Emilio Olías
Automatic Insertion of Fault-Tolerant Structures at the RT Level. IOLTW (2001)
Luis Entrena, Celia López, Emilio Olías, Enrique San Millán, José Alberto Espejo
Logic Optimization of Unidirectional Circuits with Structural Methods. IOLTW (2001)
Enrique San Millán, Luis Entrena, José Alberto Espejo
On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization. DSD (2001)
José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías
Functional extension of structural logic optimization techniques. ASP-DAC (2001)
Enrique San Millán, Luis Entrena, José Alberto Espejo, Silvia Chiusano, Fulvio Corno
Integrating Symbolic Techniques in ATPG-Based Sequential Logic Optimization. DATE (1999)
José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías
Logic Restructuring for MUX-Based FPGAs. EUROMICRO (1999)
Luis Entrena, Emilio Olías, Javier Uceda, José Alberto Espejo
Timing optimization by an improved redundancy addition and removal technique. EURO-DAC (1996)
Serafín Olcoz, Luis Entrena, Luis Berrojo
An effective system development environment based on VHDL prototyping. EURO-DAC (1995)
Serafín Olcoz, Luis Entrena, Luis Berrojo
VHDL virtual prototyping. RSP (1995)
Luis Entrena, Kwang-Ting Cheng
Sequential logic optimization by redundancy addition and removal. ICCAD (1993)