Luis Ángel García-Astudillo

Publication Activity (10 Years)

Years Active: 2020-2024
Publications (10 Years): 4

Top Topics

Redundancy Reduction

Error Minimization

Hardware Designs

Formal Verification

Top Venues

IEEE Trans. Aerosp. Electron. Syst.

Publications

Luis Ángel García-Astudillo, Almudena Lindoso, Luis Entrena
Error Mitigation Using Optimized Redundancy for Composite Algorithms in FPGAs. IEEE Trans. Aerosp. Electron. Syst. 60 (2) (2024)
Luis Entrena, Antonio J. Sanchez-Clemente, Luis Ángel García-Astudillo, Marta Portela-García, Mario García-Valderas, Almudena Lindoso, Roberto Sarmiento
Formal Verification of Fault-Tolerant Hardware Designs. IEEE Access 11 (2023)
Luis Ángel García-Astudillo, Luis Entrena, Almudena Lindoso, Honorio Martín
Reduced Resolution Redundancy: A Novel Approximate Error Mitigation Technique. IEEE Access 10 (2022)
Luis Ángel García-Astudillo, Almudena Lindoso, Marta Portela, Luis Entrena
Evaluation of a Reduced Precision Redundancy FFT Design. DCIS (2020)