José Alberto Espejo

Publication Activity (10 Years)

Years Active: 1996-2008
Publications (10 Years): 0

Publications

Enrique San Millán, Luis Entrena, José Alberto Espejo
Logic Transformations by Multiple Wire Network Addition. DSD (2008)
Enrique San Millán, Luis Entrena, José Alberto Espejo, Celia López
Theoretical comparison between sequential redundancy addition and removal and retiming optimization techniques. J. Syst. Archit. 49 (12-15) (2003)
José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías
Generalized reasoning scheme for redundancy addition and removal logic optimization. DATE (2001)
Enrique San Millán, Luis Entrena, José Alberto Espejo
On the Optimization Power of Redundancy Addition and Removal Techniques for Sequential Circuits. ICCAD (2001)
Luis Entrena, Celia López, Emilio Olías, Enrique San Millán, José Alberto Espejo
Logic Optimization of Unidirectional Circuits with Structural Methods. IOLTW (2001)
Enrique San Millán, Luis Entrena, José Alberto Espejo
On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization. DSD (2001)
José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías
Functional extension of structural logic optimization techniques. ASP-DAC (2001)
Enrique San Millán, Luis Entrena, José Alberto Espejo, Silvia Chiusano, Fulvio Corno
Integrating Symbolic Techniques in ATPG-Based Sequential Logic Optimization. DATE (1999)
José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías
Logic Restructuring for MUX-Based FPGAs. EUROMICRO (1999)
Luis Entrena, Emilio Olías, Javier Uceda, José Alberto Espejo
Timing optimization by an improved redundancy addition and removal technique. EURO-DAC (1996)