Enrique San Millán

Publication Activity (10 Years)

Years Active: 1999-2023
Publications (10 Years): 6

Top Topics

Sampling Strategies

Power Consumption

Ionizing Radiation

Top Venues

IEEE Trans. Ind. Informatics

IEICE Electron. Express

IEEE Trans. Inf. Forensics Secur.

Publications

Lozada D. Randy, Betancourt P. Juan Sebastián, Enrique San Millán
Time Synchronization Technique Hardware Implementation for OFDM Systems With Hermitian Symmetry for VLC Applications. IEEE Access 11 (2023)
Jose A. Belloch, Germán León, José M. Badía, Almudena Lindoso, Enrique San Millán
Evaluating the computational performance of the Xilinx Ultrascale+ EG Heterogeneous MPSoC. J. Supercomput. 77 (2) (2021)
Honorio Martín, Enrique San Millán, Luis Entrena-Arrontes
Dynamic control of entropy and power consumption in TRNGs for IoT applications. IEICE Electron. Express 15 (2) (2018)
Honorio Martín, Pedro Peris-López, Enrique San Millán, Juan E. Tapiador
A lightweight implementation of the Tav-128 hash function. IEICE Electron. Express 14 (11) (2017)
Honorio Martín, Pedro Peris-Lopez, Juan E. Tapiador, Enrique San Millán
A New TRNG Based on Coherent Sampling With Self-Timed Rings. IEEE Trans. Ind. Informatics 12 (1) (2016)
Honorio Martín, Thomas Korak, Enrique San Millán, Michael Hutter
Fault Attacks on STRNGs: Impact of Glitches, Temperature, and Underpowering on Randomness. IEEE Trans. Inf. Forensics Secur. 10 (2) (2015)
Honorio Martín, Pedro Peris-Lopez, Juan E. Tapiador, Enrique San Millán
An Estimator for the ASIC Footprint Area of Lightweight Cryptographic Algorithms. IEEE Trans. Ind. Informatics 10 (2) (2014)
Honorio Martín, Anna Vaskova, Celia López-Ongil, Enrique San Millán, Marta Portela-García
Effect of ionizing radiation on TRNGs for safe telecommunications: Robustness and randomness. IOLTS (2014)
Anna Vaskova, Celia López-Ongil, Enrique San Millán, Alejandro Jiménez-Horas, Luis Entrena
Accelerating secure circuit design with hardware implementation of Diehard Battery of tests of randomness. IOLTS (2011)
Honorio Martín, Enrique San Millán, Luis Entrena, Julio César Hernández Castro, Pedro Peris-Lopez
AKARI-X: A pseudorandom number generator for secure lightweight systems. IOLTS (2011)
Anna Vaskova, Celia López-Ongil, Alejandro Jiménez-Horas, Enrique San Millán, Luis Entrena
Robust cryptographic ciphers with on-line statistical properties validation. IOLTS (2010)
Pedro Peris-Lopez, Enrique San Millán, Jan C. A. van der Lubbe, Luis Entrena
Cryptographically secure pseudo-random bit generator for RFID tags. ICITST (2010)
Pedro Peris-Lopez, Julio C. Hernandez-Castro, Juan M. Estévez-Tapiador, Enrique San Millán, Jan C. A. van der Lubbe
Security Flaws in an Efficient Pseudo-Random Number Generator for Low-Power Environments. SEWCN (2009)
Alejandro Jiménez-Horas, Enrique San Millán, Celia López-Ongil, Marta Portela-García, Mario García-Valderas, Luis Entrena
Pseudo-random number generation applied to robust modern cryptography: A new technique for block ciphers. IOLTS (2009)
Celia López-Ongil, Alejandro Jiménez-Horas, Marta Portela-García, Mario García-Valderas, Enrique San Millán, Luis Entrena
Smart Hardening for Round-based Encryption Algorithms: Application to Advanced Encryption Standard. IOLTS (2008)
Enrique San Millán, Luis Entrena, José Alberto Espejo
Logic Transformations by Multiple Wire Network Addition. DSD (2008)
Almudena Lindoso, Luis Entrena, Judith Liu-Jimenez, Enrique San Millán
Correlation-Based Fingerprint Matching with Orientation Field Alignment. ICB (2007)
Michael G. Lorenz, Luis Mengibar, Enrique San Millán, Luis Entrena
Low power data processing system with self-reconfigurable architecture. J. Syst. Archit. 53 (9) (2007)
Enrique San Millán, Luis Entrena, José Alberto Espejo, Celia López
Theoretical comparison between sequential redundancy addition and removal and retiming optimization techniques. J. Syst. Archit. 49 (12-15) (2003)
José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías
Generalized reasoning scheme for redundancy addition and removal logic optimization. DATE (2001)
Enrique San Millán, Luis Entrena, José Alberto Espejo
On the Optimization Power of Redundancy Addition and Removal Techniques for Sequential Circuits. ICCAD (2001)
Luis Entrena, Celia López, Emilio Olías, Enrique San Millán, José Alberto Espejo
Logic Optimization of Unidirectional Circuits with Structural Methods. IOLTW (2001)
Enrique San Millán, Luis Entrena, José Alberto Espejo
On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization. DSD (2001)
José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías
Functional extension of structural logic optimization techniques. ASP-DAC (2001)
Enrique San Millán, Luis Entrena, José Alberto Espejo, Silvia Chiusano, Fulvio Corno
Integrating Symbolic Techniques in ATPG-Based Sequential Logic Optimization. DATE (1999)
José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías
Logic Restructuring for MUX-Based FPGAs. EUROMICRO (1999)