A 630 Mbps non-binary LDPC decoder for FPGA.
Jesus Omar LacruzFrancisco Garcia-HerreroMa José CanetJavier VallsAsuncion Perez-PascualPublished in: ISCAS (2015)
Keyphrases
- non binary
- ldpc codes
- decoding algorithm
- low density parity check
- constraint satisfaction problems
- hardware implementation
- field programmable gate array
- fpga implementation
- binary representation
- vlsi architecture
- arc consistency
- constraint propagation
- frequent pattern mining
- error correction
- distributed source coding
- turbo codes
- global constraints
- data mining
- bayesian inference
- message passing
- low complexity
- constraint satisfaction
- np complete