New hardware-efficient algorithm and architecture for the computation of 2-D DCT on a linear systolic array.
Shen-Fu HsiaoWei-Ren ShiuePublished in: ICASSP (1999)
Keyphrases
- real time
- systolic array
- optimal solution
- computational complexity
- single pass
- np hard
- vlsi implementation
- hardware architecture
- k means
- dynamic programming
- integer arithmetic
- detection algorithm
- probabilistic model
- hardware implementation
- database systems
- image segmentation
- learning algorithm
- vlsi architecture
- pipeline architecture
- linear systems
- parallel implementation
- parallel processing
- computationally efficient
- expectation maximization
- higher order
- object oriented