Yun-Nan Chang

Publication Activity (10 Years)

Years Active: 1996-2023
Publications (10 Years): 7

Top Topics

Biologically Motivated

Vlsi Architecture

Vector Graphics

Top Venues

Publications

Yun-Nan Chang
Design of Low-cost IOU Circuit for Post-processing of Object Detection. GCCE (2023)
Yun-Nan Chang, Guan-Jhen Chen
Design of A Bit-Serial Artificial Neuron VLSI Architecture with Early Termination. ICEIC (2019)
Yun-Nan Chang, Yu-Tang Tin
Scaling Bit-Flexible Neural Networks. ISOCC (2019)
Yun-Nan Chang, Chin-Lun Yang
A fast ray tracing scheme for dynamic scenes. CoDIT (2017)
Yun-Nan Chang
Design of an area-efficient partial-sum architecture for polar decoders based on new matrix generator. NEWCAS (2016)
Hsu-Kang Dow, Ching-Hua Huang, Chun-Hung Lai, Kai-Hsiang Tsao, Sheng-Chih Tseng, Kun-Yi Wu, Ting-Hsuan Wu, Ho-Chun Yang, Da-Jing Zhang-Jian, Yun-Nan Chang, Steve Haga, Shen-Fu Hsiao, Ing-Jer Huang, Shiann-Rong Kuang, Chung-Nan Lee
An OpenGL ES 2.0 3D graphics SoC with versatile HW/SW development support. VLSI-DAT (2015)
Yun-Nan Chang, Ting-Chi Tong
An Efficient Curve-Scanline Intersection Locator Design for 2D Graphics Rendering. J. Signal Process. Syst. 79 (1) (2015)
Yun-Nan Chang, Ting-Chi Tong
Design of a 2D graphics front-end rendering processor. ASAP (2014)
Ting-Chi Tong, Yun-Nan Chang
Efficient Vector Graphics Rasterization Accelerator Using Optimized Scan-Line Buffer. IEEE Trans. Very Large Scale Integr. Syst. 21 (7) (2013)
Yun-Nan Chang
Two-level hierarchical fill-buffer for graphics rendering systems. NEWCAS (2013)
Yun-Nan Chang, Keshab K. Parhi
Architectures for digital filters using stochastic computing. ICASSP (2013)
Yun-Nan Chang
A Multibank Memory-Based VLSI Architecture of DVB Symbol Deinterleaver. IEEE Trans. Very Large Scale Integr. Syst. 18 (5) (2010)
Yun-Nan Chang
Digit-Serial Pipeline Sorter Architecture. J. Signal Process. Syst. 61 (2) (2010)
Liang-Bi Chen, Ruei-Ting Gu, Wei-Sheng Huang, Chien-Chou Wang, Wen-Chi Shiue, Tsung-Yu Ho, Yun-Nan Chang, Shen-Fu Hsiao, Chung-Nan Lee, Ing-Jer Huang
An 8.69 Mvertices/s 278 Mpixels/s tile-based 3D graphics SoC HW/SW development for consumer electronics. ASP-DAC (2009)
Yun-Nan Chang
A Fast Spline Curve Rendering Accelerator Architecture. IEEE Trans. Circuits Syst. II Express Briefs (11) (2009)
Yun-Nan Chang, Ting-Chi Tong
A Lossless Buffer Compression Scheme for 3D Graphic System. CGVR (2009)
Yun-Nan Chang
A low-cost dual-mode deinterleaver design. IEEE Trans. Consumer Electron. 54 (2) (2008)
Yun-Nan Chang
An Efficient VLSI Architecture for Normal I/O Order Pipeline FFT Design. IEEE Trans. Circuits Syst. II Express Briefs (12) (2008)
Yun-Nan Chang, Ting-Chi Tong
An Efficient Design of H.264 Inter Interpolator with Bandwidth Optimization. J. Signal Process. Syst. 53 (3) (2008)
Yun-Nan Chang
Design of an efficient memory-based DVB-T channel decoder. ISCAS (5) (2005)
Yun-Nan Chang, Keshab K. Parhi
An efficient pipelined FFT architecture. IEEE Trans. Circuits Syst. II Express Briefs 50 (6) (2003)
Yun-Nan Chang
An Efficient In-Place VLSI Architecture for Viterbi Algorithm. J. VLSI Signal Process. 33 (3) (2003)
Yun-Nan Chang
Design of soft-output Viterbi decoders with hybrid trace-back processing. ISCAS (2) (2003)
Yun-Nan Chang, Hiroshi Suzuki, Keshab K. Parhi
A 2-Mb/s 256-state 10-mW rate-1/3 Viterbi decoder. IEEE J. Solid State Circuits 35 (6) (2000)
Hiroshi Suzuki, Yun-Nan Chang, Keshab K. Parhi
Low-power bit-serial Viterbi decoder for 3rd generation W-CDMA systems. CICC (1999)
Hiroshi Suzuki, Yun-Nan Chang, Keshab K. Parhi
Low-power bit-serial Viterbi decoder for next generation wide-band CDMA systems. ICASSP (1999)
Yun-Nan Chang, Keshab K. Parhi
High-performance digit-serial complex-number multiplier-accumulator. ICCD (1998)
Yun-Nan Chang, Ching-Yi Wang, Keshab K. Parhi
Heuristic Loop-Based Scheduling and Allocation for DSP Synthesis with Heterogeneous Functional Units. J. VLSI Signal Process. 19 (3) (1998)
Yun-Nan Chang, Janardhan H. Satyanarayana, Keshab K. Parhi
Design and Implementation of Low-Power Digit-Serial Multipliers. ICCD (1997)
Janardhan H. Satyanarayana, Keshab K. Parhi, Leilei Song, Yun-Nan Chang
Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers. ICCD (1996)
Yun-Nan Chang, Ching-Yi Wang, Keshab K. Parhi
Loop-List Scheduling for Heterogeneous Functional Units. Great Lakes Symposium on VLSI (1996)