An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with -55 dBc Fractional and -91 dBc Reference Spurs.
Feng-Wei KuoMasoud BabaieHuan-Neng Ron ChenLan-Chou ChoChewnpu JouMark ChenRobert Bogdan StaszewskiPublished in: IEEE Trans. Circuits Syst. I Regul. Pap. (2018)
Keyphrases