Rong-Jyi Yang

Publication Activity (10 Years)

Years Active: 2004-2016
Publications (10 Years): 1

Top Topics

Phase Locked Loop

Super Resolution

Data Conversion

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Wei-Cheng Chen, Chao-Chyun Chen, Chia-Yu Yao, Rong-Jyi Yang
A Fast-Transient Wide-Voltage-Range Digital-Controlled Buck Converter With Cycle-Controlled DPWM. IEEE Trans. Very Large Scale Integr. Syst. 24 (1) (2016)
Chia-Yu Yao, Yung-Hsiang Ho, Yi-Yao Chiu, Rong-Jyi Yang
Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line. IEEE Trans. Very Large Scale Integr. Syst. 23 (3) (2015)
Wei-Cheng Chen, Rong-Jyi Yang, Chia-Yu Yao, Chao-Chyun Chen
A wide-range all-digital delay-locked loop using fast-lock variable SAR algorithm. ISPACS (2012)
Chuan-Kang Liang, Rong-Jyi Yang, Shen-Iuan Liu
An All-Digital Fast-Locking Programmable DLL-Based Clock Generator. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2008)
Chi-Shuang Oulee, Rong-Jyi Yang
A 1.25Gbps all-digital clock and data recovery circuit with binary frequency acquisition. APCCAS (2008)
Rong-Jyi Yang, Shen-Iuan Liu
A 40-550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm. IEEE J. Solid State Circuits 42 (2) (2007)
Rong-Jyi Yang, Shen-Iuan Liu
A 2.5 GHz All-Digital Delay-Locked Loop in 0.13 µm CMOS Technology. IEEE J. Solid State Circuits 42 (11) (2007)
Rong-Jyi Yang, Kuan-Hua Chao, Sy-Chyuan Hwu, Chuan-Kang Liang, Shen-Iuan Liu
A 155.52 mbps-3.125 gbps continuous-rate clock and data recovery circuit. IEEE J. Solid State Circuits 41 (6) (2006)
Rong-Jyi Yang, Kuan-Hua Chao, Shen-Iuan Liu
A 200-Mbps∼2-Gbps continuous-rate clock-and-data-recovery circuit. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2006)
Rong-Jyi Yang, Shen-Iuan Liu
A Fully Integrated 1.7-3.125 Gbps Clock and Data Recovery Circuit Using a Gated Frequency Detector. IEICE Trans. Electron. (8) (2005)
Rong-Jyi Yang, Shen-Iuan Liu
A Wide-Range Multiphase Delay-Locked Loop Using Mixed-Mode VCDLs. IEICE Trans. Electron. (6) (2005)
Hsiang-Hui Chang, Rong-Jyi Yang, Shen-Iuan Liu
Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2004)
Rong-Jyi Yang, Shang-Ping Chen, Shen-Iuan Liu
A 3.125-Gb/s clock and data recovery circuit for the 10-Gbase-LX4 Ethernet. IEEE J. Solid State Circuits 39 (8) (2004)