Yung-Hsiang Ho

Publication Activity (10 Years)

Years Active: 2012-2016
Publications (10 Years): 2

Top Topics

Multiresolution

Digital Content

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Yung-Hsiang Ho, Chia-Yu Yao
A Low-Jitter Fast-Locked All-Digital Phase-Locked Loop With Phase-Frequency-Error Compensation. IEEE Trans. Very Large Scale Integr. Syst. 24 (5) (2016)
Yung-Hsiang Ho, Chia-Yu Yao
A Fast-Acquisition All-Digital Delay-Locked Loop Using a Starting-Bit Prediction Algorithm for the Successive-Approximation Register. IEEE Trans. Very Large Scale Integr. Syst. 24 (2) (2016)
Chia-Yu Yao, Yung-Hsiang Ho, Wei-Chun Hsia, Jyun-Jie Huang
Simulating delta-sigma analog-to-digital converters with the Op-Amp nonlinearity using the Newton's method. ISCAS (2015)
Chia-Yu Yao, Yung-Hsiang Ho, Yi-Yao Chiu, Rong-Jyi Yang
Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line. IEEE Trans. Very Large Scale Integr. Syst. 23 (3) (2015)
Chia-Yu Yao, Wei-Chun Hsia, Yung-Hsiang Ho
Designing Hardware-Efficient Fixed-Point FIR Filters in an Expanding Subexpression Space. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2014)
Chia-Yu Yao, Yung-Hsiang Ho
A fast-locking wide-range all-digital delay-locked loop with a starting SAR-bit prediction mechanism. VLSI-DAT (2013)
Chia-Yu Yao, Yung-Hsiang Ho, Wei-Chun Hsia
Optimization of the hybrid asymmetric-FIR/analog square-root filters. ISPACS (2012)