A 40-550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm.
Rong-Jyi YangShen-Iuan LiuPublished in: IEEE J. Solid State Circuits (2007)
Keyphrases
- times faster
- learning algorithm
- preprocessing
- dynamic programming
- computational complexity
- search space
- high accuracy
- k means
- significant improvement
- cost function
- experimental evaluation
- recognition algorithm
- clustering method
- simulated annealing
- worst case
- optimal solution
- computational cost
- np hard
- multiresolution
- search algorithm
- expectation maximization
- optimization algorithm
- similarity measure
- genetic algorithm